{"id":"https://openalex.org/W2997000344","doi":"https://doi.org/10.1109/iscas45731.2020.9181274","title":"Using Reduced Graphs for Efficient HLS Scheduling","display_name":"Using Reduced Graphs for Efficient HLS Scheduling","publication_year":2020,"publication_date":"2020-09-29","ids":{"openalex":"https://openalex.org/W2997000344","doi":"https://doi.org/10.1109/iscas45731.2020.9181274","mag":"2997000344"},"language":"en","primary_location":{"id":"doi:10.1109/iscas45731.2020.9181274","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas45731.2020.9181274","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://scholarworks.rit.edu/theses/10311","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5034465540","display_name":"Stephanie Soldavini","orcid":"https://orcid.org/0000-0001-7379-8007"},"institutions":[{"id":"https://openalex.org/I155173764","display_name":"Rochester Institute of Technology","ror":"https://ror.org/00v4yb702","country_code":"US","type":"education","lineage":["https://openalex.org/I155173764"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Stephanie Soldavini","raw_affiliation_strings":["Department of Computer Engineering, Rochester Institute of Technology, Rochester, NY, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Rochester Institute of Technology, Rochester, NY, USA","institution_ids":["https://openalex.org/I155173764"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044497499","display_name":"Sonia L\u00f3pez Alarc\u00f3n","orcid":"https://orcid.org/0000-0002-9130-2797"},"institutions":[{"id":"https://openalex.org/I155173764","display_name":"Rochester Institute of Technology","ror":"https://ror.org/00v4yb702","country_code":"US","type":"education","lineage":["https://openalex.org/I155173764"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sonia L\u00f3pez Alarc\u00f3n","raw_affiliation_strings":["Department of Computer Engineering, Rochester Institute of Technology, Rochester, NY, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Rochester Institute of Technology, Rochester, NY, USA","institution_ids":["https://openalex.org/I155173764"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071708090","display_name":"Marcin \u0141ukowiak","orcid":null},"institutions":[{"id":"https://openalex.org/I155173764","display_name":"Rochester Institute of Technology","ror":"https://ror.org/00v4yb702","country_code":"US","type":"education","lineage":["https://openalex.org/I155173764"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Marcin \u0141ukowiak","raw_affiliation_strings":["Department of Computer Engineering, Rochester Institute of Technology, Rochester, NY, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Rochester Institute of Technology, Rochester, NY, USA","institution_ids":["https://openalex.org/I155173764"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5034465540"],"corresponding_institution_ids":["https://openalex.org/I155173764"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":{"value":0.01480333,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"32","issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8220199346542358},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6915884613990784},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.6017480492591858},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5911083817481995},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.5567337870597839},{"id":"https://openalex.org/keywords/data-flow-analysis","display_name":"Data-flow analysis","score":0.470193475484848},{"id":"https://openalex.org/keywords/two-level-scheduling","display_name":"Two-level scheduling","score":0.45715540647506714},{"id":"https://openalex.org/keywords/dynamic-priority-scheduling","display_name":"Dynamic priority scheduling","score":0.4555342197418213},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.3855583369731903},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3595813512802124},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.3105981945991516},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.29555588960647583},{"id":"https://openalex.org/keywords/data-flow-diagram","display_name":"Data flow diagram","score":0.2328105866909027},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.15325289964675903}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8220199346542358},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6915884613990784},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.6017480492591858},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5911083817481995},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.5567337870597839},{"id":"https://openalex.org/C88468194","wikidata":"https://www.wikidata.org/wiki/Q1172416","display_name":"Data-flow analysis","level":3,"score":0.470193475484848},{"id":"https://openalex.org/C119948110","wikidata":"https://www.wikidata.org/wiki/Q7858726","display_name":"Two-level scheduling","level":4,"score":0.45715540647506714},{"id":"https://openalex.org/C107568181","wikidata":"https://www.wikidata.org/wiki/Q5319000","display_name":"Dynamic priority scheduling","level":3,"score":0.4555342197418213},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.3855583369731903},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3595813512802124},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.3105981945991516},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.29555588960647583},{"id":"https://openalex.org/C489000","wikidata":"https://www.wikidata.org/wiki/Q747385","display_name":"Data flow diagram","level":2,"score":0.2328105866909027},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.15325289964675903},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/iscas45731.2020.9181274","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas45731.2020.9181274","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},{"id":"pmh:oai:scholarworks.rit.edu:theses-11462","is_oa":true,"landing_page_url":"https://scholarworks.rit.edu/theses/10311","pdf_url":"https://scholarworks.rit.edu/theses/10311","source":{"id":"https://openalex.org/S4306402456","display_name":"RIT Scholar Works (Rochester Institute of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I155173764","host_organization_name":"Rochester Institute of Technology","host_organization_lineage":["https://openalex.org/I155173764"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Theses","raw_type":"text"},{"id":"pmh:oai:repository.rit.edu:theses-11462","is_oa":false,"landing_page_url":"https://repository.rit.edu/theses/10311","pdf_url":null,"source":{"id":"https://openalex.org/S4306402456","display_name":"RIT Scholar Works (Rochester Institute of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I155173764","host_organization_name":"Rochester Institute of Technology","host_organization_lineage":["https://openalex.org/I155173764"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Theses","raw_type":"text"}],"best_oa_location":{"id":"pmh:oai:scholarworks.rit.edu:theses-11462","is_oa":true,"landing_page_url":"https://scholarworks.rit.edu/theses/10311","pdf_url":"https://scholarworks.rit.edu/theses/10311","source":{"id":"https://openalex.org/S4306402456","display_name":"RIT Scholar Works (Rochester Institute of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I155173764","host_organization_name":"Rochester Institute of Technology","host_organization_lineage":["https://openalex.org/I155173764"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Theses","raw_type":"text"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2997000344.pdf","grobid_xml":"https://content.openalex.org/works/W2997000344.grobid-xml"},"referenced_works_count":15,"referenced_works":["https://openalex.org/W1553486105","https://openalex.org/W1970032753","https://openalex.org/W2057204501","https://openalex.org/W2071189607","https://openalex.org/W2072396657","https://openalex.org/W2147088458","https://openalex.org/W2171318521","https://openalex.org/W2183824811","https://openalex.org/W2343695530","https://openalex.org/W2475663704","https://openalex.org/W2785313678","https://openalex.org/W2798697879","https://openalex.org/W2800690434","https://openalex.org/W3006580740","https://openalex.org/W6686078825"],"related_works":["https://openalex.org/W3036719625","https://openalex.org/W2010484697","https://openalex.org/W2545511463","https://openalex.org/W2372008037","https://openalex.org/W2184166483","https://openalex.org/W2978148977","https://openalex.org/W2106332846","https://openalex.org/W1545991362","https://openalex.org/W2365679959","https://openalex.org/W2134269501"],"abstract_inverted_index":{"High-Level":[0],"Synthesis":[1],"(HLS)":[2],"is":[3,23,48],"the":[4,16,27,33,45,63,68,77,100,105,118,131],"process":[5,47],"of":[6,15,32,67,79,117,127],"generating":[7],"digital":[8],"circuits":[9],"from":[10],"high-level":[11],"algorithmic":[12],"descriptions.":[13],"One":[14],"major":[17],"steps":[18],"in":[19,38,82],"this":[20,54],"design":[21],"approach":[22,60],"scheduling,":[24,80],"which":[25,39],"uses":[26],"Control/Data":[28],"Flow":[29],"Graph":[30],"(CDFG)":[31],"software":[34],"code":[35],"and":[36,50,86,121],"determines":[37],"order":[40],"operations":[41],"must":[42],"occur.":[43],"Traditionally,":[44],"scheduling":[46,65],"time":[49,101],"memory":[51,84,119],"intensive.":[52],"In":[53],"paper,":[55],"we":[56],"present":[57],"a":[58,112],"new":[59,73],"to":[61,103,125],"replace":[62],"conventional":[64],"portion":[66],"HLS":[69],"tool":[70],"chain.":[71],"This":[72],"technique":[74],"significantly":[75],"reduces":[76],"complexity":[78],"resulting":[81],"improved":[83],"usage":[85],"lower":[87],"computational":[88],"effort.":[89],"The":[90],"results":[91],"demonstrate":[92],"that":[93],"an":[94],"average":[95],"16":[96],"times":[97],"speedup":[98],"on":[99,115,130],"required":[102],"determine":[104],"schedule":[106],"can":[107],"be":[108],"achieved,":[109],"with":[110,122],"just":[111],"fraction":[113],"(1/5":[114],"average)":[116],"usage,":[120],"only":[123],"0":[124],"6%":[126],"added":[128],"cost":[129],"final":[132],"hardware":[133],"execution":[134],"time.":[135]},"counts_by_year":[],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
