{"id":"https://openalex.org/W3090215376","doi":"https://doi.org/10.1109/iscas45731.2020.9181127","title":"Robust Dual Mode Pass Logic (DMPL) for Energy Efficiency and High Performance","display_name":"Robust Dual Mode Pass Logic (DMPL) for Energy Efficiency and High Performance","publication_year":2020,"publication_date":"2020-09-29","ids":{"openalex":"https://openalex.org/W3090215376","doi":"https://doi.org/10.1109/iscas45731.2020.9181127","mag":"3090215376"},"language":"en","primary_location":{"id":"doi:10.1109/iscas45731.2020.9181127","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas45731.2020.9181127","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088097531","display_name":"Inbal Stanger","orcid":"https://orcid.org/0000-0002-9038-1278"},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Inbal Stanger","raw_affiliation_strings":["Bar-Ilan University, Ramat Gan, Israel"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Bar-Ilan University, Ramat Gan, Israel","institution_ids":["https://openalex.org/I13955877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043898382","display_name":"Netanel Shavit","orcid":"https://orcid.org/0000-0003-2011-6329"},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Netanel Shavit","raw_affiliation_strings":["Bar-Ilan University, Ramat Gan, Israel"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Bar-Ilan University, Ramat Gan, Israel","institution_ids":["https://openalex.org/I13955877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004107991","display_name":"Ramiro Taco","orcid":"https://orcid.org/0000-0003-3046-2364"},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]},{"id":"https://openalex.org/I69094615","display_name":"Universidad San Francisco de Quito","ror":"https://ror.org/01r2c3v86","country_code":"EC","type":"education","lineage":["https://openalex.org/I69094615"]}],"countries":["EC","IL"],"is_corresponding":false,"raw_author_name":"Ramiro Taco","raw_affiliation_strings":["Bar-Ilan University, Ramat Gan, Israel; Universidad San Francisco de Quito, Quito, Ecuador"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Bar-Ilan University, Ramat Gan, Israel; Universidad San Francisco de Quito, Quito, Ecuador","institution_ids":["https://openalex.org/I13955877","https://openalex.org/I69094615"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007161424","display_name":"Leonid Yavits","orcid":"https://orcid.org/0000-0001-5248-3997"},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Leonid Yavits","raw_affiliation_strings":["Bar-Ilan University, Ramat Gan, Israel"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Bar-Ilan University, Ramat Gan, Israel","institution_ids":["https://openalex.org/I13955877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016654766","display_name":"Marco Lanuzza","orcid":"https://orcid.org/0000-0002-6480-9218"},"institutions":[{"id":"https://openalex.org/I45204951","display_name":"University of Calabria","ror":"https://ror.org/02rc97e94","country_code":"IT","type":"education","lineage":["https://openalex.org/I45204951"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Marco Lanuzza","raw_affiliation_strings":["University of Calabria, Cosenza, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Calabria, Cosenza, Italy","institution_ids":["https://openalex.org/I45204951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065902823","display_name":"Alexander Fish","orcid":"https://orcid.org/0000-0002-4994-1536"},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Alexander Fish","raw_affiliation_strings":["Bar-Ilan University, Ramat Gan, Israel"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Bar-Ilan University, Ramat Gan, Israel","institution_ids":["https://openalex.org/I13955877"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.7467955946922302},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6683160662651062},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6416993141174316},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.6370646953582764},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.6121016144752502},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5843490362167358},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5815372467041016},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.5770419836044312},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5470144152641296},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.4998307228088379},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.4959336221218109},{"id":"https://openalex.org/keywords/energy-consumption","display_name":"Energy consumption","score":0.48516160249710083},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.44342154264450073},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.43225014209747314},{"id":"https://openalex.org/keywords/threshold-voltage","display_name":"Threshold voltage","score":0.43061214685440063},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3656880259513855},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2993405759334564}],"concepts":[{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.7467955946922302},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6683160662651062},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6416993141174316},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.6370646953582764},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.6121016144752502},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5843490362167358},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5815372467041016},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.5770419836044312},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5470144152641296},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.4998307228088379},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.4959336221218109},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.48516160249710083},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.44342154264450073},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.43225014209747314},{"id":"https://openalex.org/C195370968","wikidata":"https://www.wikidata.org/wiki/Q1754002","display_name":"Threshold voltage","level":4,"score":0.43061214685440063},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3656880259513855},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2993405759334564},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas45731.2020.9181127","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas45731.2020.9181127","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.9100000262260437}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1974982221","https://openalex.org/W2037299409","https://openalex.org/W2038049046","https://openalex.org/W2127656032","https://openalex.org/W2138308719","https://openalex.org/W2141849037","https://openalex.org/W2185598583","https://openalex.org/W2509037689","https://openalex.org/W2791224953","https://openalex.org/W2904320587","https://openalex.org/W2916239311"],"related_works":["https://openalex.org/W2082591327","https://openalex.org/W2580743037","https://openalex.org/W2029162371","https://openalex.org/W4324145463","https://openalex.org/W4324145462","https://openalex.org/W2074886140","https://openalex.org/W2167525841","https://openalex.org/W2045384631","https://openalex.org/W2096750766","https://openalex.org/W4250383491"],"abstract_inverted_index":{"In":[0,54],"the":[1,22,34,46,83,100,117],"past,":[2],"Pass":[3,66],"Transistor":[4],"Logic":[5,67,105],"(PTL)":[6],"was":[7],"widely":[8],"used":[9],"due":[10],"to":[11,41,82,92,107,109,116,147],"benefits":[12],"in":[13,50,128],"terms":[14],"of":[15,25,48,102,156,163],"speed":[16,73,111,171],"and":[17,38,74,95,139,143,186],"power":[18,76,96,140],"consumption":[19,77,97],"coming":[20],"from":[21],"reduced":[23],"number":[24],"transistors.":[26],"However,":[27],"issues":[28],"such":[29],"as":[30,145,180],"threshold":[31],"drop":[32],"across":[33],"single-channel":[35],"pass":[36],"transistors":[37],"high":[39,72],"sensitivity":[40],"process":[42,185],"variations":[43,188],"have":[44],"prevented":[45],"use":[47],"PTL":[49,91],"advanced":[51],"nanometer":[52],"technologies.":[53],"this":[55],"paper,":[56],"we":[57],"propose":[58],"a":[59,110,157],"novel":[60],"logic":[61],"family":[62],"named":[63],"Dual":[64,103],"Mode":[65,104],"(DMPL),":[68],"which":[69],"allows":[70],"for":[71],"low":[75],"while":[78],"maintaining":[79],"robustness":[80,179],"down":[81],"sub-threshold":[84],"voltage":[85],"region.":[86],"The":[87],"DMPL":[88,135,158,175],"effectively":[89],"combines":[90],"reduce":[93,137],"energy":[94,138],"along":[98],"with":[99],"flexibility":[101],"(DML)":[106],"switch":[108],"improved":[112],"operating":[113],"mode":[114],"according":[115],"system":[118],"requirement.":[119],"Simulation":[120],"analysis":[121],"performed":[122],"on":[123],"basic":[124],"NOR/NAND":[125],"gates":[126,176],"implemented":[127],"16":[129],"nm":[130],"Finfet":[131],"technology":[132],"demonstrates":[133],"that":[134,162],"can":[136,160],"by":[141,168],"33%":[142],"42%":[144],"compared":[146],"logically":[148],"equivalent":[149],"static":[150,165,181],"CMOS":[151,166,182],"design.":[152],"Moreover,":[153],"running":[154],"frequency":[155],"circuit":[159],"exceed":[161],"its":[164],"counterpart":[167],"84%":[169],"when":[170],"is":[172],"mandatory.":[173],"Additionally,":[174],"demonstrate":[177],"similar":[178],"implementations":[183],"under":[184],"temperature":[187],"at":[189],"lower":[190],"supply":[191],"voltages.":[192]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2021,"cited_by_count":1}],"updated_date":"2026-07-22T07:51:19.307946","created_date":"2025-10-10T00:00:00"}