{"id":"https://openalex.org/W3090816752","doi":"https://doi.org/10.1109/iscas45731.2020.9181020","title":"MINT: Mixed-Precision RRAM-Based IN-Memory Training Architecture","display_name":"MINT: Mixed-Precision RRAM-Based IN-Memory Training Architecture","publication_year":2020,"publication_date":"2020-09-29","ids":{"openalex":"https://openalex.org/W3090816752","doi":"https://doi.org/10.1109/iscas45731.2020.9181020","mag":"3090816752"},"language":"en","primary_location":{"id":"doi:10.1109/iscas45731.2020.9181020","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas45731.2020.9181020","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5013020304","display_name":"Hongwu Jiang","orcid":"https://orcid.org/0000-0002-3048-5948"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hongwu Jiang","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA","School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014877058","display_name":"Shanshi Huang","orcid":"https://orcid.org/0000-0002-1760-7656"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shanshi Huang","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA","School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076031530","display_name":"Xiaochen Peng","orcid":"https://orcid.org/0000-0001-6148-7711"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xiaochen Peng","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA","School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5054894631","display_name":"Shimeng Yu","orcid":"https://orcid.org/0000-0002-0068-3652"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shimeng Yu","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA","School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I130701444"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":28,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.7370588779449463},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7216447591781616},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4905657172203064},{"id":"https://openalex.org/keywords/convolutional-neural-network","display_name":"Convolutional neural network","score":0.4820359945297241},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4674689769744873},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.4150850176811218},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.4149400591850281},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.40975096821784973},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.39341825246810913},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3573736846446991},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.2829993665218353},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.20254454016685486},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10923519730567932},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.0885169506072998}],"concepts":[{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.7370588779449463},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7216447591781616},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4905657172203064},{"id":"https://openalex.org/C81363708","wikidata":"https://www.wikidata.org/wiki/Q17084460","display_name":"Convolutional neural network","level":2,"score":0.4820359945297241},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4674689769744873},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.4150850176811218},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.4149400591850281},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.40975096821784973},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.39341825246810913},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3573736846446991},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.2829993665218353},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.20254454016685486},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10923519730567932},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0885169506072998},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas45731.2020.9181020","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas45731.2020.9181020","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8999999761581421,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1686810756","https://openalex.org/W2025535306","https://openalex.org/W2248832573","https://openalex.org/W2289252105","https://openalex.org/W2508602506","https://openalex.org/W2518281301","https://openalex.org/W2606722458","https://openalex.org/W2782046614","https://openalex.org/W2787513570","https://openalex.org/W2794194363","https://openalex.org/W2798554798","https://openalex.org/W2805362231","https://openalex.org/W2913035851","https://openalex.org/W2921329602","https://openalex.org/W2921351161","https://openalex.org/W2943765373","https://openalex.org/W2962835968","https://openalex.org/W2964164125","https://openalex.org/W2966199719","https://openalex.org/W2982974103","https://openalex.org/W6637373629","https://openalex.org/W6748319235"],"related_works":["https://openalex.org/W2545245183","https://openalex.org/W2054635671","https://openalex.org/W2017425642","https://openalex.org/W2350916061","https://openalex.org/W2952918855","https://openalex.org/W1970117475","https://openalex.org/W4396815615","https://openalex.org/W3161624601","https://openalex.org/W2078381924","https://openalex.org/W4381388454"],"abstract_inverted_index":{"On-chip":[0],"training":[1,42,122,129],"of":[2,118,131],"large-scale":[3],"deep":[4],"neural":[5],"networks":[6],"(DNNs)":[7],"is":[8,18,108,124],"challenging.":[9],"To":[10],"solve":[11],"the":[12,24,28,34,75,79,85,105,128,137,164],"memory":[13,29,112],"wall":[14],"problem,":[15],"compute-in-memory":[16],"(CIM)":[17],"a":[19,58,132],"promising":[20],"approach":[21],"that":[22,63,114,149],"exploits":[23],"analog":[25],"computation":[26],"inside":[27],"array":[30],"to":[31],"speed":[32],"up":[33],"vector-matrix":[35],"multiplication":[36],"(VMM).":[37],"Challenges":[38],"for":[39,101],"on-chip":[40,69],"CIM":[41,61,98,166],"include":[43],"higher":[44,48,175],"weight":[45,77,106],"precision":[46],"and":[47,67,84,92,158,178],"analog-to-digital":[49],"converter":[50],"(ADC)":[51],"resolution.":[52],"In":[53,71],"this":[54,141],"work,":[55],"we":[56,73],"propose":[57],"mixed-precision":[59],"RRAM-based":[60],"architecture":[62],"overcomes":[64],"these":[65],"challenges":[66],"supports":[68],"training.":[70],"particular,":[72],"split":[74],"multi-bit":[76],"into":[78],"most":[80],"significant":[81,87],"bits":[82,88],"(MSBs)":[83],"least":[86],"(LSBs).":[89],"The":[90],"forward":[91],"backward":[93],"propagations":[94],"are":[95],"performed":[96,109],"with":[97,163],"transposable":[99],"arrays":[100,113],"MSBs":[102],"only,":[103],"while":[104],"update":[107],"in":[110],"regular":[111],"store":[115],"LSBs.":[116],"Impact":[117],"ADC":[119],"resolution":[120],"on":[121,136,169],"accuracy":[123,154],"analyzed.":[125],"We":[126],"explore":[127],"performance":[130],"convolutional":[133],"VGG-like":[134],"network":[135],"CIFAR-10":[138],"dataset":[139],"using":[140],"Mixed-precision":[142],"IN-memory":[143],"Training":[144],"architecture,":[145],"namely":[146],"MINT,":[147],"showing":[148],"it":[150,171],"can":[151,172],"achieve":[152,173],"~91%":[153],"under":[155],"hardware":[156],"constraints":[157],"~4.46TOPS/W":[159],"energy":[160,176],"efficiency.":[161],"Compared":[162],"baseline":[165],"architectures":[167],"based":[168],"RRAM,":[170],"1.35\u00d7":[174],"efficiency":[177],"only":[179],"31.9%":[180],"chip":[181],"size":[182],"(~98.86":[183],"mm2at":[184],"32":[185],"nm":[186],"node).":[187]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":6},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":7},{"year":2021,"cited_by_count":8},{"year":2020,"cited_by_count":2}],"updated_date":"2026-07-29T09:40:50.615796","created_date":"2025-10-10T00:00:00"}
