{"id":"https://openalex.org/W3091603505","doi":"https://doi.org/10.1109/iscas45731.2020.9180699","title":"A Semiparallel Full-Adder in IMPLY Logic","display_name":"A Semiparallel Full-Adder in IMPLY Logic","publication_year":2020,"publication_date":"2020-09-29","ids":{"openalex":"https://openalex.org/W3091603505","doi":"https://doi.org/10.1109/iscas45731.2020.9180699","mag":"3091603505"},"language":"en","primary_location":{"id":"doi:10.1109/iscas45731.2020.9180699","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas45731.2020.9180699","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063322669","display_name":"Shokat Ganjeheizadeh Rohani","orcid":null},"institutions":[{"id":"https://openalex.org/I133738476","display_name":"University of Massachusetts Lowell","ror":"https://ror.org/03hamhx47","country_code":"US","type":"education","lineage":["https://openalex.org/I133738476"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Shokat Ganjeheizadeh Rohani","raw_affiliation_strings":["Department of Electrical &#x0026; Computer Engineering, University of Massachusetts Lowell, Lowell, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical &#x0026; Computer Engineering, University of Massachusetts Lowell, Lowell, USA","institution_ids":["https://openalex.org/I133738476"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103899686","display_name":"Nima Taheri Nejad","orcid":null},"institutions":[{"id":"https://openalex.org/I145847075","display_name":"TU Wien","ror":"https://ror.org/04d836q62","country_code":"AT","type":"education","lineage":["https://openalex.org/I145847075"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Nima Taheri Nejad","raw_affiliation_strings":["Institute of Computer Technology, TU Wien, Vienna, Austria","Institute of Computer Technology, Tech. Univ. Wien, Vienna, Austria"],"affiliations":[{"raw_affiliation_string":"Institute of Computer Technology, TU Wien, Vienna, Austria","institution_ids":["https://openalex.org/I145847075"]},{"raw_affiliation_string":"Institute of Computer Technology, Tech. Univ. Wien, Vienna, Austria","institution_ids":["https://openalex.org/I145847075"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5075635327","display_name":"David Radakovits","orcid":null},"institutions":[{"id":"https://openalex.org/I145847075","display_name":"TU Wien","ror":"https://ror.org/04d836q62","country_code":"AT","type":"education","lineage":["https://openalex.org/I145847075"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"David Radakovits","raw_affiliation_strings":["Institute of Computer Technology, TU Wien, Vienna, Austria","Institute of Computer Technology, Tech. Univ. Wien, Vienna, Austria"],"affiliations":[{"raw_affiliation_string":"Institute of Computer Technology, TU Wien, Vienna, Austria","institution_ids":["https://openalex.org/I145847075"]},{"raw_affiliation_string":"Institute of Computer Technology, Tech. Univ. Wien, Vienna, Austria","institution_ids":["https://openalex.org/I145847075"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5063322669"],"corresponding_institution_ids":["https://openalex.org/I133738476"],"apc_list":null,"apc_paid":null,"fwci":0.2055,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.51554356,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":"17","issue":null,"first_page":"1","last_page":"1"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9943000078201294,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.7754080295562744},{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.6795414090156555},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6708654165267944},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.6358839869499207},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5428221225738525},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.47369813919067383},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4725577235221863},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.47191765904426575},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3860738277435303},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.38349002599716187},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.377468079328537},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.32545334100723267},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.24900862574577332},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2377791404724121},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.216469407081604},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1592940092086792},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14679905772209167},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08240821957588196}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.7754080295562744},{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.6795414090156555},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6708654165267944},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.6358839869499207},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5428221225738525},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.47369813919067383},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4725577235221863},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.47191765904426575},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3860738277435303},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.38349002599716187},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.377468079328537},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.32545334100723267},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.24900862574577332},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2377791404724121},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.216469407081604},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1592940092086792},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14679905772209167},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08240821957588196},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas45731.2020.9180699","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas45731.2020.9180699","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.5099999904632568}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2213903980","https://openalex.org/W1966764473","https://openalex.org/W2082788688","https://openalex.org/W1488117239","https://openalex.org/W2373127312","https://openalex.org/W378890350","https://openalex.org/W659242671","https://openalex.org/W2098419840","https://openalex.org/W2386022279","https://openalex.org/W2766377030"],"abstract_inverted_index":{"Passive":[0],"implementation":[1,44,121],"of":[2,13,38,45,61,67,78,134,188,225,233,243,274,326,333,352,379,389,522,535],"memristors":[3,23,234,327,361,401],"has":[4,126],"led":[5,374],"to":[6,26,117,158,169,175,182,213,263,375,392,415,497,517,525,549,563],"several":[7,30,52],"innovative":[8],"works":[9,384,552],"in":[10,29,87,191,196,217,228,257,280,296,307,312,387,397,443,465,477,501,513,546,569],"the":[11,39,43,62,68,76,102,130,135,138,141,176,189,197,200,231,241,272,275,303,319,324,331,340,343,353,406,411,446,475,498,520,542,570],"field":[12],"electronics.":[14],"Despite":[15],"being":[16],"primarily":[17],"a":[18,79,148,152,186,218,223,371,376,393,469,494],"candidate":[19],"for":[20,96,120,151,342,365,404,440,451,468],"memory":[21],"applications,":[22,442],"have":[24],"proven":[25],"be":[27,118,211,288,459],"beneficial":[28],"other":[31,550],"circuits":[32,47],"and":[33,65,89,99,107,137,204,240,265,268,330,362,418,454,488,565],"applications":[34],"as":[35,49,113,314,316,435],"well.":[36],"One":[37],"use":[40],"cases":[41],"is":[42,59,85,91,156,300,328,335,338,350,437,449,538,560],"digital":[46,153],"such":[48,112],"adders.":[50],"Among":[51],"logic":[53,58],"implementations":[54],"using":[55,122],"memristors,":[56],"IMPLY":[57,80,106],"one":[60,66,351],"promising":[63],"candidates":[64],"first":[69,320,355],"stateful":[70],"logics":[71],"proposed.":[72],"In":[73,143,180,318,346,369],"this":[74,144,428,536],"logic,":[75,109],"result":[77,408],"b":[81,88],"(a":[82],"\u2192":[83],"b)":[84],"stored":[86],"it":[90],"always":[92],"true":[93],"(1)":[94],"except":[95],"when":[97,445],"a=0":[98],"b=1.":[100],"Given":[101],"intrinsic":[103],"difference":[104],"between":[105],"Boolean":[108],"conventional":[110],"operations":[111,453],"binary":[114],"addition":[115,181],"need":[116],"appropriated":[119],"IMPLY.":[123],"This":[124,337],"appropriation":[125],"two":[127,291,510],"main":[128],"constituents;":[129],"topology":[131],"or":[132,208],"structure":[133],"adder":[136],"algorithm":[139,373,413],"performing":[140],"addition.":[142,368],"paper,":[145],"we":[146,184,221,254,515],"proposed":[147,396,464,479,545],"new":[149,394,412],"architecture":[150],"full-adder,":[154],"which":[155,194,229,297,308,358,430,482,559],"up":[157,168],"41%":[159],"faster":[160],"than":[161,541],"existing":[162,177],"IMPLY-based":[163,192,285],"serial":[164,347,511,526,551],"designs":[165,216,281],"while":[166],"requiring":[167],"78%":[170],"less":[171],"area":[172,264],"(memristors)":[173],"compared":[174,562],"parallel":[178,313,462,543,571],"design.":[179],"that,":[183],"present":[185],"review":[187],"state-of-the-art":[190],"adders,":[193,348],"appeared":[195],"literature":[198],"during":[199],"last":[201],"five":[202],"years":[203],"discuss":[205],"their":[206],"advantages":[207],"disadvantages.":[209],"To":[210],"able":[212],"compare":[214],"these":[215],"generic":[219],"condition,":[220],"define":[222],"Figure":[224],"Merit":[226],"(FoM),":[227],"both":[230],"number":[232,242,325,332,378,521],"(n":[235,245],"<sub":[236,246,485],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[237,247,486],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">m</sub>":[238,487],")":[239,249],"steps":[244,334,364,523],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">s</sub>":[248],"are":[250,310],"equally":[251],"important.":[252],"However,":[253,427],"must":[255,457],"bear":[256],"mind":[258],"that":[259],"m":[260,417],"(which":[261,270],"translates":[262],"consequently":[266,419],"cost)":[267],"s":[269],"represents":[271],"speed":[273],"full-adder)":[276],"carry":[277],"different":[278,283,372],"weights":[279],"with":[282],"constraints.":[284],"adders":[286],"can":[287],"divided":[289],"into":[290],"major":[292],"micro-architectures;":[293],"i)":[294],"serial,":[295],"each":[298],"bit":[299],"processed":[301],"after":[302],"other,":[304],"ii)":[305],"parallel,":[306,514],"bits":[309],"added":[311],"long":[315,470],"possible.":[317],"category,":[321],"relatively":[322],"speaking,":[323],"low":[329],"high.":[336],"quite":[339],"opposite":[341],"second":[344],"category.":[345],"[1]":[349,466],"very":[354],"efficient":[356],"designs,":[357],"needs":[359,555],"3n+3":[360],"29n":[363],"an":[366,480],"n-bit":[367],"[2],":[370],"smaller":[377],"steps,":[380],"i.e.,":[381],"23n.":[382],"These":[383],"were":[385,402],"improved":[386,490],"terms":[388],"FoM,":[390,421],"thanks":[391],"approach":[395,544],"[3],":[398],"where":[399],"input":[400,448],"used":[403],"storing":[405],"output":[407],"too.":[409],"Thus,":[410],"managed":[414,516],"reduce":[416,519],"increase":[420],"without":[422,528],"needing":[423,529],"any":[424,530],"structural":[425],"changes.":[426],"approach,":[429,481],"was":[431,467],"adopted":[432],"by":[433,492,508],"[4]":[434,478],"well,":[436],"not":[438,458],"suitable":[439],"all":[441],"particular":[444],"respective":[447],"needed":[450],"further":[452],"its":[455],"value":[456],"lost.":[460],"The":[461,533],"design":[463,537,554],"time":[471],"uncontested":[472],"until":[473],"recently":[474],"authors":[476],"reduced":[483],"n":[484,566],"thus":[489],"FoM":[491,534],"applying":[493],"minimal":[495],"change":[496],"structure.":[499],"Lastly,":[500],"our":[502,553],"newer":[503],"topology,":[504,507],"namely":[505],"semiparallel":[506],"having":[509],"sections":[512],"considerably":[518],"(compared":[524],"adders),":[527],"additional":[531],"memristors.":[532],"even":[539],"better":[540],"[4].":[547],"Compared":[548],"three":[556],"extra":[557],"switches,":[558],"negligible":[561],"2n":[564],"switches":[567],"required":[568],"approaches.":[572]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}