{"id":"https://openalex.org/W3090716251","doi":"https://doi.org/10.1109/iscas45731.2020.9180588","title":"Fast Packet Classification using RISC-V and HyperSplit Acceleration on FPGA","display_name":"Fast Packet Classification using RISC-V and HyperSplit Acceleration on FPGA","publication_year":2020,"publication_date":"2020-09-29","ids":{"openalex":"https://openalex.org/W3090716251","doi":"https://doi.org/10.1109/iscas45731.2020.9180588","mag":"3090716251"},"language":"en","primary_location":{"id":"doi:10.1109/iscas45731.2020.9180588","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas45731.2020.9180588","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075996278","display_name":"Arsinoe Pnevmatikou","orcid":null},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Arsinoe Pnevmatikou","raw_affiliation_strings":["School of Electrical and Computer Engineering, National Technical University of Athens, Greece","School of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, National Technical University of Athens, Greece","institution_ids":["https://openalex.org/I174458059"]},{"raw_affiliation_string":"School of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece","institution_ids":["https://openalex.org/I174458059"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053524294","display_name":"George Lentaris","orcid":"https://orcid.org/0000-0003-1664-8648"},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"George Lentaris","raw_affiliation_strings":["School of Electrical and Computer Engineering, National Technical University of Athens, Greece","School of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, National Technical University of Athens, Greece","institution_ids":["https://openalex.org/I174458059"]},{"raw_affiliation_string":"School of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece","institution_ids":["https://openalex.org/I174458059"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043131021","display_name":"Dimitrios Soudris","orcid":"https://orcid.org/0000-0002-6930-6847"},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Dimitrios Soudris","raw_affiliation_strings":["School of Electrical and Computer Engineering, National Technical University of Athens, Greece","School of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, National Technical University of Athens, Greece","institution_ids":["https://openalex.org/I174458059"]},{"raw_affiliation_string":"School of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece","institution_ids":["https://openalex.org/I174458059"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002743530","display_name":"Nikos Kokkalis","orcid":null},"institutions":[{"id":"https://openalex.org/I86100027","display_name":"Intracom Telecom (Greece)","ror":"https://ror.org/04npy5k94","country_code":"GR","type":"company","lineage":["https://openalex.org/I86100027"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Nikos Kokkalis","raw_affiliation_strings":["Intracom Telecom, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intracom Telecom, Greece","institution_ids":["https://openalex.org/I86100027"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6762,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.63032469,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"2","issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10400","display_name":"Network Security and Intrusion Detection","score":0.9868999719619751,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10714","display_name":"Software-Defined Networks and 5G","score":0.9796000123023987,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7631269097328186},{"id":"https://openalex.org/keywords/acceleration","display_name":"Acceleration","score":0.753675103187561},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7157095074653625},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.5306823253631592},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.38842183351516724},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3767232298851013},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.23789703845977783},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.08240821957588196}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7631269097328186},{"id":"https://openalex.org/C117896860","wikidata":"https://www.wikidata.org/wiki/Q11376","display_name":"Acceleration","level":2,"score":0.753675103187561},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7157095074653625},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.5306823253631592},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.38842183351516724},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3767232298851013},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.23789703845977783},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.08240821957588196},{"id":"https://openalex.org/C74650414","wikidata":"https://www.wikidata.org/wiki/Q11397","display_name":"Classical mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas45731.2020.9180588","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas45731.2020.9180588","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.6200000047683716,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W79029001","https://openalex.org/W1975959118","https://openalex.org/W2026164946","https://openalex.org/W2105838178","https://openalex.org/W2137145600","https://openalex.org/W2139587756","https://openalex.org/W2139751271","https://openalex.org/W2150702922","https://openalex.org/W2154770818","https://openalex.org/W2159669151","https://openalex.org/W2170694613","https://openalex.org/W2536297326","https://openalex.org/W6603209019"],"related_works":["https://openalex.org/W2002703587","https://openalex.org/W2580284127","https://openalex.org/W2955742250","https://openalex.org/W2147062161","https://openalex.org/W2086302072","https://openalex.org/W1549901675","https://openalex.org/W1675622250","https://openalex.org/W1988547703","https://openalex.org/W3011931499","https://openalex.org/W2811290777"],"abstract_inverted_index":{"Performance":[0],"demands":[1],"in":[2,99],"communications":[3],"technology":[4],"is":[5,42],"driving":[6],"research":[7,55],"towards":[8],"advanced":[9],"network":[10,75],"processors,":[11],"which":[12],"are":[13],"able":[14],"to":[15,52,69,73,89,125,135],"handle":[16],"huge":[17],"rates":[18],"of":[19,29,40,112],"incoming":[20],"packets":[21],"via":[22,77],"application-specific":[23],"circuits,":[24],"however,":[25],"without":[26],"sacrificing":[27],"all":[28],"the":[30,35,38,44,58,60,83,109],"conventional":[31],"CPU":[32],"flexibility.":[33],"At":[34],"same":[36],"time,":[37],"advent":[39],"RISC-V":[41,71,130],"disrupting":[43],"industry":[45],"&":[46],"academia":[47],"by":[48],"opening":[49],"computer":[50],"architecture":[51],"a":[53,70,86],"broader":[54],"community.":[56],"Combining":[57],"above,":[59],"current":[61],"paper":[62],"considers":[63],"placing":[64],"dedicated":[65],"VHDL":[66],"accelerators":[67],"next":[68],"processor":[72],"accommodate":[74],"functions":[76],"customized":[78],"HW/SW":[79],"co-processing.":[80],"We":[81],"extend":[82],"ISA":[84],"with":[85],"new":[87],"instruction":[88],"perform":[90],"search":[91,111],"tree":[92],"operations":[93],"that":[94],"accelerate":[95],"Packet":[96],"Classification":[97],"tasks":[98],"routers.":[100],"For":[101],"rapid":[102],"prototyping":[103],"and":[104,132],"design":[105,122],"exploration,":[106],"we":[107],"implement":[108],"binary":[110],"HyperSplit":[113],"algorithm":[114],"on":[115],"an":[116],"Xilinx":[117],"Ultrascale":[118],"xcku060":[119],"FPGA.":[120],"Our":[121],"achieves":[123],"up":[124,134],"118\u00d7":[126],"faster":[127],"classification":[128],"than":[129],"alone":[131],"sustains":[133],"25.4M":[136],"packets/sec":[137],"throughput.":[138]},"counts_by_year":[{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}