{"id":"https://openalex.org/W3091332734","doi":"https://doi.org/10.1109/iscas45731.2020.9180537","title":"Calibration of Capacitor Mismatch and Static Comparator Offset in SAR ADC with Digital Redundancy","display_name":"Calibration of Capacitor Mismatch and Static Comparator Offset in SAR ADC with Digital Redundancy","publication_year":2020,"publication_date":"2020-09-29","ids":{"openalex":"https://openalex.org/W3091332734","doi":"https://doi.org/10.1109/iscas45731.2020.9180537","mag":"3091332734"},"language":"en","primary_location":{"id":"doi:10.1109/iscas45731.2020.9180537","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas45731.2020.9180537","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078655536","display_name":"Antonio Lopez-Angulo","orcid":"https://orcid.org/0000-0002-4548-3638"},"institutions":[{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]},{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Antonio Lopez-Angulo","raw_affiliation_strings":["Instituto de Microelectr&#x00F3;nica de Sevilla IMSE-CNM (CSIC - Universidad de Sevilla), Av. Am&#x00E9;rico Vespucio, 28. 41092, Seville, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Microelectr&#x00F3;nica de Sevilla IMSE-CNM (CSIC - Universidad de Sevilla), Av. Am&#x00E9;rico Vespucio, 28. 41092, Seville, Spain","institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072282417","display_name":"Antonio Gin\u00e9s","orcid":"https://orcid.org/0000-0001-5272-5802"},"institutions":[{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]},{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Antonio Gines","raw_affiliation_strings":["Instituto de Microelectr&#x00F3;nica de Sevilla IMSE-CNM (CSIC - Universidad de Sevilla), Av. Am&#x00E9;rico Vespucio, 28. 41092, Seville, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Microelectr&#x00F3;nica de Sevilla IMSE-CNM (CSIC - Universidad de Sevilla), Av. Am&#x00E9;rico Vespucio, 28. 41092, Seville, Spain","institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091600572","display_name":"E. Peral\u00edas","orcid":"https://orcid.org/0000-0003-0629-0785"},"institutions":[{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]},{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Eduardo Peralias","raw_affiliation_strings":["Instituto de Microelectr&#x00F3;nica de Sevilla IMSE-CNM (CSIC - Universidad de Sevilla), Av. Am&#x00E9;rico Vespucio, 28. 41092, Seville, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Microelectr&#x00F3;nica de Sevilla IMSE-CNM (CSIC - Universidad de Sevilla), Av. Am&#x00E9;rico Vespucio, 28. 41092, Seville, Spain","institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.3533,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.79232044,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.8399718999862671},{"id":"https://openalex.org/keywords/comparator","display_name":"Comparator","score":0.7599859237670898},{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.732820451259613},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.7203365564346313},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6708492040634155},{"id":"https://openalex.org/keywords/successive-approximation-adc","display_name":"Successive approximation ADC","score":0.6468607187271118},{"id":"https://openalex.org/keywords/calibration","display_name":"Calibration","score":0.4775317907333374},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44873717427253723},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2328098714351654},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18560948967933655},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1282653510570526},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11194422841072083}],"concepts":[{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.8399718999862671},{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.7599859237670898},{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.732820451259613},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.7203365564346313},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6708492040634155},{"id":"https://openalex.org/C60154766","wikidata":"https://www.wikidata.org/wiki/Q2650458","display_name":"Successive approximation ADC","level":4,"score":0.6468607187271118},{"id":"https://openalex.org/C165838908","wikidata":"https://www.wikidata.org/wiki/Q736777","display_name":"Calibration","level":2,"score":0.4775317907333374},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44873717427253723},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2328098714351654},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18560948967933655},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1282653510570526},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11194422841072083},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas45731.2020.9180537","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas45731.2020.9180537","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1584667699","https://openalex.org/W1806621776","https://openalex.org/W2027349025","https://openalex.org/W2042702103","https://openalex.org/W2078717740","https://openalex.org/W2080031036","https://openalex.org/W2106988548","https://openalex.org/W2143690596","https://openalex.org/W2275716794","https://openalex.org/W2474323687","https://openalex.org/W2535745143","https://openalex.org/W2592800647","https://openalex.org/W2742121197","https://openalex.org/W2744967592","https://openalex.org/W2802326377","https://openalex.org/W2802617484","https://openalex.org/W2898006859","https://openalex.org/W2899238293","https://openalex.org/W3024999395","https://openalex.org/W6634913629","https://openalex.org/W6657252809","https://openalex.org/W6694593497"],"related_works":["https://openalex.org/W2278942241","https://openalex.org/W2368405386","https://openalex.org/W1977749038","https://openalex.org/W2082979872","https://openalex.org/W1641489184","https://openalex.org/W2136440001","https://openalex.org/W2135250276","https://openalex.org/W3004044036","https://openalex.org/W2792167570","https://openalex.org/W1965493748"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,12,51,71,85,104],"robust":[4],"method":[5,96],"to":[6,38,50],"perform":[7],"capacitor":[8,33],"mismatch":[9],"calibration":[10,25],"in":[11,23,81,84,103],"redundant":[13,112],"SAR":[14,106],"ADCs":[15],"correcting":[16],"the":[17,24,41,60,76,82,95],"effect":[18],"of":[19,30,40,94],"comparator":[20],"static":[21],"offset":[22,90],"process.":[26],"Without":[27],"proper":[28],"handling":[29],"this":[31,66,68],"effect,":[32],"miscalibration":[34],"can":[35],"occur":[36],"due":[37],"saturation":[39],"redundancy":[42,88],"intervals":[43],"associated":[44],"with":[45,55,87,110],"implemented":[46],"weights,":[47],"eventually":[48],"leading":[49],"faulty":[52],"behavior":[53],"even":[54],"lower":[56],"effective":[57],"resolution":[58],"than":[59],"case":[61,108],"without":[62],"calibration.":[63],"To":[64],"overcome":[65],"limitation,":[67],"work":[69],"proposes":[70],"foreground":[72],"technique":[73],"which":[74],"reuses":[75],"least-significant":[77],"bit":[78],"(LSB)":[79],"capacitors":[80],"array":[83],"design":[86],"for":[89],"compensation.":[91],"The":[92],"effectiveness":[93],"is":[97],"demonstrated":[98],"by":[99],"realistic":[100],"behavioral":[101],"simulations":[102],"12-bit":[105],"ADC":[107],"study":[109],"3":[111],"bits.":[113]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2020,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
