{"id":"https://openalex.org/W2942818097","doi":"https://doi.org/10.1109/iscas.2019.8702551","title":"Toward In-System Monitoring of OpenCL-Based Designs on FPGA","display_name":"Toward In-System Monitoring of OpenCL-Based Designs on FPGA","publication_year":2019,"publication_date":"2019-05-01","ids":{"openalex":"https://openalex.org/W2942818097","doi":"https://doi.org/10.1109/iscas.2019.8702551","mag":"2942818097"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2019.8702551","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2019.8702551","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5023126187","display_name":"Hachem Bensalem","orcid":"https://orcid.org/0000-0001-9713-2410"},"institutions":[{"id":"https://openalex.org/I9736820","display_name":"\u00c9cole de Technologie Sup\u00e9rieure","ror":"https://ror.org/0020snb74","country_code":"CA","type":"education","lineage":["https://openalex.org/I49663120","https://openalex.org/I9736820"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Hachem Bensalem","raw_affiliation_strings":["Department of Electrical Engineering, \u00c9cole de Tehnologie Sup\u00e9rieure, Montreal, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, \u00c9cole de Tehnologie Sup\u00e9rieure, Montreal, Canada","institution_ids":["https://openalex.org/I9736820"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071840145","display_name":"Yves Blaqui\u00e8re","orcid":"https://orcid.org/0000-0001-6204-7427"},"institutions":[{"id":"https://openalex.org/I9736820","display_name":"\u00c9cole de Technologie Sup\u00e9rieure","ror":"https://ror.org/0020snb74","country_code":"CA","type":"education","lineage":["https://openalex.org/I49663120","https://openalex.org/I9736820"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Yves Blaquiere","raw_affiliation_strings":["Department of Electrical Engineering, \u00c9cole de Tehnologie Sup\u00e9rieure, Montreal, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, \u00c9cole de Tehnologie Sup\u00e9rieure, Montreal, Canada","institution_ids":["https://openalex.org/I9736820"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038488044","display_name":"Yvon Savaria","orcid":"https://orcid.org/0000-0002-3404-9959"},"institutions":[{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Yvon Savaria","raw_affiliation_strings":["Department of Electrical Engineering, Ecole Polytechnique, Montreal, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Ecole Polytechnique, Montreal, Canada","institution_ids":["https://openalex.org/I45683168"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5023126187"],"corresponding_institution_ids":["https://openalex.org/I9736820"],"apc_list":null,"apc_paid":null,"fwci":0.7405,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.67628448,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8643689751625061},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7955993413925171},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.597362220287323},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.5499569177627563},{"id":"https://openalex.org/keywords/kernel","display_name":"Kernel (algebra)","score":0.4725218415260315},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4422803223133087},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.15053236484527588}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8643689751625061},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7955993413925171},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.597362220287323},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.5499569177627563},{"id":"https://openalex.org/C74193536","wikidata":"https://www.wikidata.org/wiki/Q574844","display_name":"Kernel (algebra)","level":2,"score":0.4725218415260315},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4422803223133087},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.15053236484527588},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/iscas.2019.8702551","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2019.8702551","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},{"id":"pmh:oai:espace2.etsmtl.ca:19983","is_oa":false,"landing_page_url":"http://espace2.etsmtl.ca/id/eprint/19983/","pdf_url":null,"source":{"id":"https://openalex.org/S4306402392","display_name":"Espace \u00c9TS (ETS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1341030882","host_organization_name":"Educational Testing Service","host_organization_lineage":["https://openalex.org/I1341030882"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Compte rendu de conf\u00e9rence"},{"id":"pmh:oai:publications.polymtl.ca:43531","is_oa":false,"landing_page_url":"https://publications.polymtl.ca/43531/","pdf_url":null,"source":{"id":"https://openalex.org/S4306401013","display_name":"PolyPublie (\u00c9cole Polytechnique de Montr\u00e9al)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I45683168","host_organization_name":"Polytechnique Montr\u00e9al","host_organization_lineage":["https://openalex.org/I45683168"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Communication de conf\u00e9rence"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320310709","display_name":"CMC Microsystems","ror":"https://ror.org/03k70ea39"},{"id":"https://openalex.org/F4320334350","display_name":"High Performance Research Computing, Texas A and M University","ror":null},{"id":"https://openalex.org/F4320334593","display_name":"Natural Sciences and Engineering Research Council of Canada","ror":"https://ror.org/01h531d29"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W48450883","https://openalex.org/W594283781","https://openalex.org/W1978408137","https://openalex.org/W1992364842","https://openalex.org/W2000921084","https://openalex.org/W2090808187","https://openalex.org/W2092185683","https://openalex.org/W2157993125","https://openalex.org/W2166029537","https://openalex.org/W2218038495","https://openalex.org/W2257686317","https://openalex.org/W2317369144","https://openalex.org/W2343695530","https://openalex.org/W2602914815","https://openalex.org/W2624897816","https://openalex.org/W6601971408","https://openalex.org/W6692159191","https://openalex.org/W6735686474"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2355315220","https://openalex.org/W4200391368","https://openalex.org/W2210979487","https://openalex.org/W2074043759","https://openalex.org/W2316202402","https://openalex.org/W2096844293","https://openalex.org/W2363944576","https://openalex.org/W2351041855","https://openalex.org/W2570254841"],"abstract_inverted_index":{"This":[0,15],"paper":[1],"presents":[2],"a":[3,142],"new":[4],"in-system":[5,117],"circuit":[6,16,140],"for":[7,20,128,148],"monitoring":[8,22,28,118,139],"and":[9,41,60,123],"profiling":[10],"OpenCL-based":[11,24,53],"designs":[12],"on":[13],"FPGA.":[14],"opens":[17],"the":[18,89,100,104,115,120,129,137],"door":[19],"improved":[21],"of":[23],"FPGA":[25,91,122],"accelerators.":[26],"The":[27,47,132],"approach":[29],"allows":[30],"designers":[31],"to":[32,107],"identify":[33],"unexpected":[34],"performance":[35],"bottlenecks":[36],"such":[37,111],"as":[38],"pipeline":[39],"stalls":[40],"initiation":[42],"interval":[43],"in":[44,70,82,110],"OpenCL":[45,72,130,164],"loops.":[46],"proposed":[48,116],"monitor":[49,79,94],"enhances":[50],"observability":[51],"into":[52],"accelerators":[54],"by":[55,77],"capturing":[56],"high-level":[57],"hardware":[58],"events":[59],"timing":[61],"information":[62],"at":[63],"FPGA-clock":[64],"accuracy.":[65],"Any":[66],"event":[67],"or":[68],"variable":[69],"an":[71],"kernel":[73],"can":[74,96],"be":[75,108],"observed":[76],"instantiating":[78],"circuits":[80],"specified":[81],"OpenCL.":[83],"To":[84,113],"our":[85],"knowledge,":[86],"it":[87],"is":[88],"first":[90],"clock-cycle":[92],"accurate":[93],"that":[95,136,145],"select":[97],"not":[98],"only":[99],"variables,":[101],"but":[102],"also":[103],"data":[105],"inputs":[106],"monitored":[109],"variables.":[112],"validate":[114],"circuit,":[119],"Arria10":[121],"Intel":[124],"SDK":[125],"were":[126],"used":[127],"tool-chain.":[131],"reported":[133,163],"results":[134],"show":[135],"presented":[138],"introduces":[141],"frequency":[143],"degradation":[144],"remains":[146],"small":[147],"8":[149],"tested":[150],"monitors":[151,154],"instances.":[152],"These":[153],"use":[155],"2.3":[156],"times":[157],"fewer":[158],"logic":[159],"resources":[160],"than":[161],"previously":[162],"monitors.":[165]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
