{"id":"https://openalex.org/W2943227047","doi":"https://doi.org/10.1109/iscas.2019.8702538","title":"Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores","display_name":"Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores","publication_year":2019,"publication_date":"2019-05-01","ids":{"openalex":"https://openalex.org/W2943227047","doi":"https://doi.org/10.1109/iscas.2019.8702538","mag":"2943227047"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2019.8702538","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2019.8702538","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5085694093","display_name":"Lu\u00eds Fiolhais","orcid":"https://orcid.org/0000-0002-5629-9465"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Luis Fiolhais","raw_affiliation_strings":["INESC-ID/IST, Lisboa"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INESC-ID/IST, Lisboa","institution_ids":["https://openalex.org/I121345201"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067214457","display_name":"F.M. Gon\u00e7alves","orcid":"https://orcid.org/0000-0002-0559-1888"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Fernando Goncalves","raw_affiliation_strings":["INESC-ID/IST, Lisboa"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INESC-ID/IST, Lisboa","institution_ids":["https://openalex.org/I121345201"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079441335","display_name":"Rui Policarpo Duarte","orcid":"https://orcid.org/0000-0002-7060-4745"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Rui P. Duarte","raw_affiliation_strings":["INESC-ID/IST, Lisboa"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INESC-ID/IST, Lisboa","institution_ids":["https://openalex.org/I121345201"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003178960","display_name":"M\u00e1rio V\u00e9stias","orcid":"https://orcid.org/0000-0001-8556-4507"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Mario Vestias","raw_affiliation_strings":["INESC-ID/ISEL"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INESC-ID/ISEL","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043958334","display_name":"Jos\u00e9 T. de Sousa","orcid":"https://orcid.org/0000-0001-7525-7546"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Jose T. de Sousa","raw_affiliation_strings":["INESC-ID/IST, Lisboa"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INESC-ID/IST, Lisboa","institution_ids":["https://openalex.org/I121345201"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7465365529060364},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.5632264018058777},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5584955811500549},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5041667222976685},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42926791310310364},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.1841486096382141}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7465365529060364},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.5632264018058777},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5584955811500549},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5041667222976685},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42926791310310364},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.1841486096382141}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2019.8702538","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2019.8702538","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},{"id":"pmh:oai:repositorio.ipl.pt:10400.21/9965","is_oa":false,"landing_page_url":"http://hdl.handle.net/10400.21/9965","pdf_url":null,"source":{"id":"https://openalex.org/S4306402433","display_name":"Portuguese National Funding Agency for Science, Research and Technology (RCAAP Project by FCT)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"conference object"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.6499999761581421,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W93901327","https://openalex.org/W1864199185","https://openalex.org/W1983394510","https://openalex.org/W2082365376","https://openalex.org/W2276486856","https://openalex.org/W2735381705","https://openalex.org/W2761881456","https://openalex.org/W2764252782","https://openalex.org/W2963255460","https://openalex.org/W6741215685","https://openalex.org/W6931260761","https://openalex.org/W6940917043"],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W2390279801","https://openalex.org/W2358668433","https://openalex.org/W2376932109","https://openalex.org/W2001405890","https://openalex.org/W2382290278","https://openalex.org/W2035206467","https://openalex.org/W2512308948","https://openalex.org/W2068921804","https://openalex.org/W4387696986"],"abstract_inverted_index":{"The":[0,88,131,152],"idea":[1],"of":[2,17,53,70,83,90,112,150,194],"combining":[3],"multiple":[4],"CPU":[5,73,89],"and":[6,20,36,58,74,124,174,182,188,202],"CGRA":[7,76,154],"cores":[8,133],"is":[9,92,155],"not":[10],"in":[11,29,104],"itself":[12],"original":[13],"but":[14],"detailed":[15],"characterizations":[16],"such":[18],"architectures":[19],"measurements":[21],"on":[22,55],"compelling":[23],"applications":[24],"are":[25,38,42,86,178],"difficult":[26],"to":[27,50,147],"find":[28],"the":[30,51,84,93,138,148,156,192,195],"literature.":[31],"Although":[32],"commercial":[33,44],"CPUs,":[34],"GPUs":[35],"FPGAs":[37],"widely":[39],"available,":[40],"there":[41],"no":[43],"CGRAs,":[45],"which":[46,99,161],"may":[47],"be":[48],"attributed":[49],"lack":[52],"metrics":[54],"performance,":[56],"energy":[57,203],"cost.":[59],"In":[60],"this":[61],"paper,":[62],"we":[63],"introduce":[64],"a":[65,116,121,125],"heterogeneous":[66],"computing":[67],"platform":[68,197],"consisting":[69],"several":[71,81],"RISC-V":[72,97,114,132],"Versat":[75,158],"cores.":[77],"Implementation":[78,168],"results":[79,169],"for":[80,143,160,170],"instances":[82,164],"architecture":[85],"presented.":[87],"choice":[91],"promising":[94],"open":[95],"source":[96],"architecture,":[98,159],"has":[100],"never":[101],"been":[102,135,166],"featured":[103],"CPU/CGRA":[105],"architectures.":[106],"This":[107],"paper":[108],"presents":[109],"independent":[110],"implementations":[111],"two":[113],"cores:":[115],"minimal":[117],"one,":[118],"useful":[119,142],"as":[120],"simple":[122],"controller,":[123],"more":[126],"performant":[127],"5-stage":[128],"pipeline":[129],"implementation.":[130],"have":[134,165],"designed":[136],"using":[137],"recent":[139],"Chisel":[140],"HDL,":[141],"automating":[144],"tasks":[145],"pertaining":[146],"writing":[149],"RTL.":[151],"selected":[153],"published":[157],"4":[162],"different":[163],"created.":[167],"2":[171],"FPGA":[172],"families":[173],"ASIC":[175],"technology":[176],"nodes":[177],"presented:":[179],"area,":[180,200],"frequency":[181,201],"power.":[183],"Applications":[184],"cover":[185],"digital":[186],"audio":[187],"machine":[189],"learning,":[190],"demonstrating":[191],"versatility":[193],"proposed":[196],"at":[198],"competitive":[199],"footprints.":[204]},"counts_by_year":[{"year":2024,"cited_by_count":3},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}