{"id":"https://openalex.org/W2943764824","doi":"https://doi.org/10.1109/iscas.2019.8702507","title":"A Novel Glitch-Free Integrated Clock Gating Cell for High Reliability","display_name":"A Novel Glitch-Free Integrated Clock Gating Cell for High Reliability","publication_year":2019,"publication_date":"2019-05-01","ids":{"openalex":"https://openalex.org/W2943764824","doi":"https://doi.org/10.1109/iscas.2019.8702507","mag":"2943764824"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2019.8702507","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2019.8702507","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082062216","display_name":"Tasnuva Noor","orcid":null},"institutions":[{"id":"https://openalex.org/I59553526","display_name":"Stony Brook University","ror":"https://ror.org/05qghxh33","country_code":"US","type":"education","lineage":["https://openalex.org/I59553526"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tasnuva Noor","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Stony Brook University (SUNY), New York"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Stony Brook University (SUNY), New York","institution_ids":["https://openalex.org/I59553526"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5061262597","display_name":"Emre Salman","orcid":"https://orcid.org/0000-0001-6538-6803"},"institutions":[{"id":"https://openalex.org/I59553526","display_name":"Stony Brook University","ror":"https://ror.org/05qghxh33","country_code":"US","type":"education","lineage":["https://openalex.org/I59553526"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Emre Salman","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Stony Brook University (SUNY), New York"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Stony Brook University (SUNY), New York","institution_ids":["https://openalex.org/I59553526"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I59553526"],"apc_list":null,"apc_paid":null,"fwci":0.7965,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.62037075,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.9260720610618591},{"id":"https://openalex.org/keywords/glitch","display_name":"Glitch","score":0.8891847133636475},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.7044919729232788},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6417723894119263},{"id":"https://openalex.org/keywords/signal-edge","display_name":"Signal edge","score":0.6262148022651672},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.617047131061554},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.5109800100326538},{"id":"https://openalex.org/keywords/gating","display_name":"Gating","score":0.5099762678146362},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.5035154223442078},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4968624413013458},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.4770716428756714},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.470549613237381},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.45684492588043213},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.42484885454177856},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.32428494095802307},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.3178524971008301},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.30442625284194946},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20504924654960632},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.1564432680606842},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.11099326610565186},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09656867384910583},{"id":"https://openalex.org/keywords/analog-signal","display_name":"Analog signal","score":0.06623190641403198}],"concepts":[{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.9260720610618591},{"id":"https://openalex.org/C191287063","wikidata":"https://www.wikidata.org/wiki/Q543281","display_name":"Glitch","level":3,"score":0.8891847133636475},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.7044919729232788},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6417723894119263},{"id":"https://openalex.org/C117525741","wikidata":"https://www.wikidata.org/wiki/Q775654","display_name":"Signal edge","level":4,"score":0.6262148022651672},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.617047131061554},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.5109800100326538},{"id":"https://openalex.org/C194544171","wikidata":"https://www.wikidata.org/wiki/Q21105679","display_name":"Gating","level":2,"score":0.5099762678146362},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.5035154223442078},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4968624413013458},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.4770716428756714},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.470549613237381},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.45684492588043213},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.42484885454177856},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32428494095802307},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3178524971008301},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.30442625284194946},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20504924654960632},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.1564432680606842},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.11099326610565186},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09656867384910583},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.06623190641403198},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C42407357","wikidata":"https://www.wikidata.org/wiki/Q521","display_name":"Physiology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2019.8702507","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2019.8702507","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.49000000953674316}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1480989605","https://openalex.org/W1990371333","https://openalex.org/W1999924508","https://openalex.org/W2029866618","https://openalex.org/W2069460396","https://openalex.org/W2087723567","https://openalex.org/W2096889604","https://openalex.org/W2097015933","https://openalex.org/W2113092930","https://openalex.org/W2113138823","https://openalex.org/W2114132980","https://openalex.org/W2120872844","https://openalex.org/W2126823681","https://openalex.org/W2144334108","https://openalex.org/W2156114993","https://openalex.org/W2247480952","https://openalex.org/W2326765630","https://openalex.org/W2533651815","https://openalex.org/W3138612623"],"related_works":["https://openalex.org/W2052455055","https://openalex.org/W2294981364","https://openalex.org/W4232628459","https://openalex.org/W2188309737","https://openalex.org/W1572462408","https://openalex.org/W2943764824","https://openalex.org/W2286776167","https://openalex.org/W2090237663","https://openalex.org/W2161776375","https://openalex.org/W1985693075"],"abstract_inverted_index":{"A":[0,43],"novel":[1],"glitch-free":[2],"integrated":[3,53],"clock":[4,29,41,54,111],"gating":[5,55],"(ICG)":[6],"cell":[7,19,49,86],"is":[8,20,57,66,87],"developed":[9],"and":[10,74],"demonstrated":[11],"in":[12,31,36,106],"45":[13,79],"nm":[14,80],"CMOS":[15,81],"technology.":[16,82],"The":[17,83],"proposed":[18,48,84],"more":[21],"reliable":[22],"as":[23,76],"it":[24],"produces":[25],"an":[26],"uninterrupted":[27],"gated":[28],"signal":[30,39,109],"cases":[32],"where":[33,98],"glitches":[34,105],"occur":[35],"the":[37,47,51,69,107],"enable":[38,108],"during":[40,110],"transitions.":[42,112],"detailed":[44],"comparison":[45],"of":[46,71],"with":[50],"existing":[52,99],"cells":[56],"also":[58],"presented.":[59],"Glitch-free":[60],"operation":[61],"(and":[62],"therefore":[63],"high":[64],"reliability)":[65],"achieved":[67],"at":[68],"expense":[70],"larger":[72],"power":[73],"delay,":[75],"quantified":[77],"for":[78],"ICG":[85],"shown":[88],"to":[89,93],"be":[90],"highly":[91],"applicable":[92],"dual":[94],"edge":[95],"triggered":[96],"flip-flops":[97],"ICGs":[100],"fail":[101],"if":[102],"there":[103],"are":[104]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}