{"id":"https://openalex.org/W2943716057","doi":"https://doi.org/10.1109/iscas.2019.8702311","title":"Self-Aligned Open-Loop Multiphase Generator","display_name":"Self-Aligned Open-Loop Multiphase Generator","publication_year":2019,"publication_date":"2019-05-01","ids":{"openalex":"https://openalex.org/W2943716057","doi":"https://doi.org/10.1109/iscas.2019.8702311","mag":"2943716057"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2019.8702311","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2019.8702311","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5003054800","display_name":"Michael Kalcher","orcid":"https://orcid.org/0000-0003-3478-5734"},"institutions":[{"id":"https://openalex.org/I4092182","display_name":"Graz University of Technology","ror":"https://ror.org/00d7xrm67","country_code":"AT","type":"education","lineage":["https://openalex.org/I4092182"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Michael Kalcher","raw_affiliation_strings":["Institute of Electronics, Graz University of Technology, Graz, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Electronics, Graz University of Technology, Graz, Austria","institution_ids":["https://openalex.org/I4092182"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5036952742","display_name":"Daniel Gruber","orcid":"https://orcid.org/0000-0003-2169-0955"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Daniel Gruber","raw_affiliation_strings":["Intel Austria, Villach, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Austria, Villach, Austria","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.7965,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.62032977,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dbc","display_name":"dBc","score":0.6855829954147339},{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.6531510949134827},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6308903694152832},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.5854076147079468},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5226687788963318},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.49432897567749023},{"id":"https://openalex.org/keywords/generator","display_name":"Generator (circuit theory)","score":0.4897737503051758},{"id":"https://openalex.org/keywords/frequency-offset","display_name":"Frequency offset","score":0.46693888306617737},{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.4632156491279602},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.451078325510025},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.40999963879585266},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.3746463656425476},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.35829800367355347},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23842653632164001},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.1437225043773651},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.11213284730911255}],"concepts":[{"id":"https://openalex.org/C193523891","wikidata":"https://www.wikidata.org/wiki/Q1771950","display_name":"dBc","level":3,"score":0.6855829954147339},{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.6531510949134827},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6308903694152832},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.5854076147079468},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5226687788963318},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.49432897567749023},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.4897737503051758},{"id":"https://openalex.org/C49319798","wikidata":"https://www.wikidata.org/wiki/Q5502874","display_name":"Frequency offset","level":4,"score":0.46693888306617737},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.4632156491279602},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.451078325510025},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.40999963879585266},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3746463656425476},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.35829800367355347},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23842653632164001},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.1437225043773651},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.11213284730911255},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C40409654","wikidata":"https://www.wikidata.org/wiki/Q375889","display_name":"Orthogonal frequency-division multiplexing","level":3,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2019.8702311","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2019.8702311","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8700000047683716}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1850342120","https://openalex.org/W1934819944","https://openalex.org/W1991961966","https://openalex.org/W1996114343","https://openalex.org/W2013788674","https://openalex.org/W2021633363","https://openalex.org/W2043454922","https://openalex.org/W2067620221","https://openalex.org/W2100869429","https://openalex.org/W2109309394","https://openalex.org/W2115427309","https://openalex.org/W2116788671","https://openalex.org/W2118016613","https://openalex.org/W2119119508","https://openalex.org/W2131340432","https://openalex.org/W2159868837","https://openalex.org/W2336452661","https://openalex.org/W2537955961","https://openalex.org/W2560308703","https://openalex.org/W2769836338","https://openalex.org/W4232117311","https://openalex.org/W4232857182","https://openalex.org/W6639006847"],"related_works":["https://openalex.org/W2540832666","https://openalex.org/W4286579627","https://openalex.org/W4392188952","https://openalex.org/W1851259350","https://openalex.org/W272184114","https://openalex.org/W2117747481","https://openalex.org/W2394282069","https://openalex.org/W3189810088","https://openalex.org/W2141726610","https://openalex.org/W2288941099"],"abstract_inverted_index":{"An":[0],"open-loop":[1],"feedback-less":[2],"CMOS":[3],"multiphase":[4,77],"generator":[5,78],"circuit":[6,34,51,116],"architecture":[7],"is":[8,52],"presented.":[9],"The":[10,28,49],"principle":[11],"generates":[12],"n":[13],"360\u00b0/n-spaced":[14],"outputs":[15],"from":[16,65,102],"a":[17,55,80,94,103],"single-ended":[18],"input":[19],"LO":[20],"or":[21],"clock":[22],"at":[23,89,107],"the":[24,32,36,40,75,111,114],"very":[25],"same":[26],"frequency.":[27],"phase":[29,47,83],"accuracy":[30],"of":[31,42,74,86,98,113],"implemented":[33],"employing":[35],"principle,":[37],"relies":[38],"on":[39],"matching":[41],"delays":[43],"and":[44],"weighted":[45],"linear":[46],"interpolation.":[48],"presented":[50,115],"designed":[53,76],"in":[54],"28":[56],"nm":[57],"bulk-CMOS":[58],"technology":[59],"covering":[60],"an":[61],"operating":[62],"frequency":[63],"range":[64],"1.5":[66],"GHz":[67],"up":[68],"to":[69],"2.5":[70],"GHz.":[71],"Simulation":[72],"results":[73],"show":[79],"worst":[81],"case":[82],"noise":[84],"performance":[85],"-151":[87],"dBc/Hz":[88],"100":[90],"MHz":[91],"offset":[92],"with":[93],"typical":[95],"power":[96],"consumption":[97],"only":[99],"3.5":[100],"mW":[101],"0.95":[104],"V":[105],"supply":[106],"2":[108],"GHz,":[109],"demonstrating":[110],"feasibility":[112],"architecture.":[117]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
