{"id":"https://openalex.org/W2943441500","doi":"https://doi.org/10.1109/iscas.2019.8702198","title":"Path-Based Statistical Static Timing Analysis for Large Integrated Circuits in a Weak Correlation Approximation","display_name":"Path-Based Statistical Static Timing Analysis for Large Integrated Circuits in a Weak Correlation Approximation","publication_year":2019,"publication_date":"2019-05-01","ids":{"openalex":"https://openalex.org/W2943441500","doi":"https://doi.org/10.1109/iscas.2019.8702198","mag":"2943441500"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2019.8702198","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2019.8702198","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/10197/9830","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088460399","display_name":"Dmytro Mishagli","orcid":"https://orcid.org/0000-0003-0712-1094"},"institutions":[{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Dmytro Mishagli","raw_affiliation_strings":["School of Electrical and Electronic Engineering, University College Dublin, Ireland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, University College Dublin, Ireland","institution_ids":["https://openalex.org/I100930933"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031376924","display_name":"Eugene Koskin","orcid":"https://orcid.org/0000-0002-4253-0312"},"institutions":[{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Eugene Koskin","raw_affiliation_strings":["School of Electrical and Electronic Engineering, University College Dublin, Ireland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, University College Dublin, Ireland","institution_ids":["https://openalex.org/I100930933"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001003834","display_name":"Elena Blokhina","orcid":"https://orcid.org/0000-0002-4164-4350"},"institutions":[{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Elena Blokhina","raw_affiliation_strings":["School of Electrical and Electronic Engineering, University College Dublin, Ireland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, University College Dublin, Ireland","institution_ids":["https://openalex.org/I100930933"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.4844,"has_fulltext":true,"cited_by_count":8,"citation_normalized_percentile":{"value":0.64838582,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7604122161865234},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.7598578333854675},{"id":"https://openalex.org/keywords/monte-carlo-method","display_name":"Monte Carlo method","score":0.6415745615959167},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6403369903564453},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.5334620475769043},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.475167453289032},{"id":"https://openalex.org/keywords/random-variable","display_name":"Random variable","score":0.4700155556201935},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4627110958099365},{"id":"https://openalex.org/keywords/scale","display_name":"Scale (ratio)","score":0.46231919527053833},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.44560280442237854},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.26118019223213196},{"id":"https://openalex.org/keywords/statistics","display_name":"Statistics","score":0.1653101146221161}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7604122161865234},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.7598578333854675},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.6415745615959167},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6403369903564453},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.5334620475769043},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.475167453289032},{"id":"https://openalex.org/C122123141","wikidata":"https://www.wikidata.org/wiki/Q176623","display_name":"Random variable","level":2,"score":0.4700155556201935},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4627110958099365},{"id":"https://openalex.org/C2778755073","wikidata":"https://www.wikidata.org/wiki/Q10858537","display_name":"Scale (ratio)","level":2,"score":0.46231919527053833},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.44560280442237854},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.26118019223213196},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.1653101146221161},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2019.8702198","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2019.8702198","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},{"id":"pmh:oai:researchrepository.ucd.ie:10197/9830","is_oa":true,"landing_page_url":"http://hdl.handle.net/10197/9830","pdf_url":"http://hdl.handle.net/10197/9830","source":{"id":"https://openalex.org/S4306402280","display_name":"Research Repository UCD (University College Dublin)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I100930933","host_organization_name":"University College Dublin","host_organization_lineage":["https://openalex.org/I100930933"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference Publication"}],"best_oa_location":{"id":"pmh:oai:researchrepository.ucd.ie:10197/9830","is_oa":true,"landing_page_url":"http://hdl.handle.net/10197/9830","pdf_url":"http://hdl.handle.net/10197/9830","source":{"id":"https://openalex.org/S4306402280","display_name":"Research Repository UCD (University College Dublin)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I100930933","host_organization_name":"University College Dublin","host_organization_lineage":["https://openalex.org/I100930933"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference Publication"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2943441500.pdf","grobid_xml":"https://content.openalex.org/works/W2943441500.grobid-xml"},"referenced_works_count":19,"referenced_works":["https://openalex.org/W581425779","https://openalex.org/W612784192","https://openalex.org/W658677875","https://openalex.org/W1483017465","https://openalex.org/W1530625153","https://openalex.org/W1967709031","https://openalex.org/W2060002782","https://openalex.org/W2143901474","https://openalex.org/W2171825402","https://openalex.org/W2398434371","https://openalex.org/W2472297161","https://openalex.org/W2482869441","https://openalex.org/W2497609193","https://openalex.org/W2504767107","https://openalex.org/W2751862591","https://openalex.org/W2753908209","https://openalex.org/W2886559659","https://openalex.org/W4231443636","https://openalex.org/W6720898181"],"related_works":["https://openalex.org/W4283025278","https://openalex.org/W61292821","https://openalex.org/W2082432309","https://openalex.org/W817174743","https://openalex.org/W2313771674","https://openalex.org/W4230512219","https://openalex.org/W4243251804","https://openalex.org/W2030835619","https://openalex.org/W1999133053","https://openalex.org/W2370249666"],"abstract_inverted_index":{"This":[0],"work":[1],"is":[2,18,48,83],"aimed":[3],"at":[4],"the":[5,24,40,59],"development":[6],"of":[7,26,43,61,65,76,80,86,91,103],"a":[8,35,52,62,73,89],"path-based":[9],"approach":[10,93],"to":[11,57],"Statistical":[12],"Static":[13],"Timing":[14,16],"Analysis.":[15],"Analysis":[17],"an":[19],"absolutely":[20],"essential":[21],"step":[22],"in":[23,50],"verification":[25],"Very":[27],"Large":[28],"Scale":[29],"Integration":[30],"(VLSI)":[31],"designs.":[32],"We":[33],"propose":[34],"novel":[36],"analytical":[37],"methodology":[38,105],"for":[39],"fast":[41],"calculations":[42],"VLSI":[44],"delay.":[45],"The":[46],"problem":[47],"stated":[49],"such":[51],"way":[53],"that":[54],"becomes":[55],"equivalent":[56],"finding":[58],"maximum":[60],"large":[63],"set":[64],"correlated":[66],"random":[67],"variables":[68],"(RVs).":[69],"For":[70],"this":[71],"purpose,":[72],"corresponding":[74],"extension":[75],"extreme":[77],"value":[78],"theory":[79],"weakly-correlated":[81],"RVs":[82],"developed.":[84],"Results":[85],"simulations":[87,97],"showing":[88],"comparison":[90],"our":[92,104],"with":[94],"Monte":[95],"Carlo":[96],"are":[98,109],"presented.":[99],"Possible":[100],"applications,":[101],"extensions":[102],"and":[106],"future":[107],"steps":[108],"discussed.":[110]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}