{"id":"https://openalex.org/W2943758646","doi":"https://doi.org/10.1109/iscas.2019.8702111","title":"SpFlow: Memory-Driven Data Flow Optimization for Sparse Matrix-Matrix Multiplication","display_name":"SpFlow: Memory-Driven Data Flow Optimization for Sparse Matrix-Matrix Multiplication","publication_year":2019,"publication_date":"2019-05-01","ids":{"openalex":"https://openalex.org/W2943758646","doi":"https://doi.org/10.1109/iscas.2019.8702111","mag":"2943758646"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2019.8702111","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2019.8702111","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101828442","display_name":"Qi Nie","orcid":"https://orcid.org/0000-0002-0254-0487"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Qi Nie","raw_affiliation_strings":["Department of Electrical Engineering, Princeton University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Princeton University","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5085975362","display_name":"Sharad Malik","orcid":"https://orcid.org/0000-0002-0837-5443"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sharad Malik","raw_affiliation_strings":["Department of Electrical Engineering, Princeton University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Princeton University","institution_ids":["https://openalex.org/I20089843"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I20089843"],"apc_list":null,"apc_paid":null,"fwci":0.2157,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.3190028,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":93},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7551876306533813},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7191276550292969},{"id":"https://openalex.org/keywords/sparse-matrix","display_name":"Sparse matrix","score":0.6573017239570618},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6247584819793701},{"id":"https://openalex.org/keywords/matrix-multiplication","display_name":"Matrix multiplication","score":0.6245467066764832},{"id":"https://openalex.org/keywords/kernel","display_name":"Kernel (algebra)","score":0.6054337024688721},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.5738792419433594},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.5609179139137268},{"id":"https://openalex.org/keywords/matrix","display_name":"Matrix (chemical analysis)","score":0.4212174415588379},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.4156855344772339},{"id":"https://openalex.org/keywords/computational-science","display_name":"Computational science","score":0.38862869143486023},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.330445259809494},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2965890169143677},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.1636870801448822},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11232215166091919}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7551876306533813},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7191276550292969},{"id":"https://openalex.org/C56372850","wikidata":"https://www.wikidata.org/wiki/Q1050404","display_name":"Sparse matrix","level":3,"score":0.6573017239570618},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6247584819793701},{"id":"https://openalex.org/C17349429","wikidata":"https://www.wikidata.org/wiki/Q1049914","display_name":"Matrix multiplication","level":3,"score":0.6245467066764832},{"id":"https://openalex.org/C74193536","wikidata":"https://www.wikidata.org/wiki/Q574844","display_name":"Kernel (algebra)","level":2,"score":0.6054337024688721},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.5738792419433594},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.5609179139137268},{"id":"https://openalex.org/C106487976","wikidata":"https://www.wikidata.org/wiki/Q685816","display_name":"Matrix (chemical analysis)","level":2,"score":0.4212174415588379},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.4156855344772339},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.38862869143486023},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.330445259809494},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2965890169143677},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.1636870801448822},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11232215166091919},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C159985019","wikidata":"https://www.wikidata.org/wiki/Q181790","display_name":"Composite material","level":1,"score":0.0},{"id":"https://openalex.org/C84114770","wikidata":"https://www.wikidata.org/wiki/Q46344","display_name":"Quantum","level":2,"score":0.0},{"id":"https://openalex.org/C163716315","wikidata":"https://www.wikidata.org/wiki/Q901177","display_name":"Gaussian","level":2,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2019.8702111","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2019.8702111","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1506342804","https://openalex.org/W1969102784","https://openalex.org/W1980282429","https://openalex.org/W1981252059","https://openalex.org/W1987225815","https://openalex.org/W1990832096","https://openalex.org/W1999085092","https://openalex.org/W2003313945","https://openalex.org/W2004455575","https://openalex.org/W2024818089","https://openalex.org/W2035080386","https://openalex.org/W2106111377","https://openalex.org/W2128539477","https://openalex.org/W2285660444","https://openalex.org/W2565851976","https://openalex.org/W2593303827","https://openalex.org/W2963674932","https://openalex.org/W4240168186","https://openalex.org/W4245683599","https://openalex.org/W4294560677","https://openalex.org/W6638632666","https://openalex.org/W6734621401"],"related_works":["https://openalex.org/W2293771254","https://openalex.org/W3121828480","https://openalex.org/W2039875226","https://openalex.org/W4221142455","https://openalex.org/W2032786851","https://openalex.org/W2914631005","https://openalex.org/W2123154672","https://openalex.org/W2952630098","https://openalex.org/W3132517792","https://openalex.org/W4285148873"],"abstract_inverted_index":{"To":[0],"improve":[1],"the":[2,31,37,74,84],"performance":[3,85],"of":[4,40],"sparse":[5],"matrix-matrix":[6],"multiplication":[7],"(SpMM)":[8],"running":[9,73],"on":[10,68,97],"a":[11,15,48,71,81],"specialized":[12],"architecture,":[13],"orchestrating":[14],"data":[16,20,50],"flow":[17,51],"that":[18],"maximizes":[19],"reuse":[21],"in":[22,78],"local":[23],"memory":[24],"is":[25],"critical":[26],"but":[27],"challenging":[28],"due":[29],"to":[30],"irregular":[32],"non-zero":[33],"element":[34],"locations":[35],"and":[36,63,91],"wide":[38],"range":[39],"sparsity.":[41],"In":[42],"this":[43],"work,":[44],"we":[45],"proposed":[46],"SpFlow,":[47],"memory-driven":[49],"optimization":[52],"framework":[53],"for":[54],"SpMM.":[55],"SpFlow":[56],"can":[57,86],"realize":[58],"54X":[59],"fewer":[60,65],"DRAM":[61],"accesses":[62,67,93],"97X":[64],"SRAM":[66,92],"average":[69],"than":[70],"GPU":[72],"cuSPARSE":[75],"kernel.":[76],"And":[77],"comparison":[79],"with":[80],"state-of-the-art":[82],"accelerator,":[83],"be":[87],"improved":[88],"by":[89,95],"3X,":[90],"reduced":[94],"5X":[96],"average.":[98]},"counts_by_year":[{"year":2021,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}