{"id":"https://openalex.org/W2943784901","doi":"https://doi.org/10.1109/iscas.2019.8701882","title":"Effect of Circuit Non-Idealities on Active On-Chip Delay Lines","display_name":"Effect of Circuit Non-Idealities on Active On-Chip Delay Lines","publication_year":2019,"publication_date":"2019-05-01","ids":{"openalex":"https://openalex.org/W2943784901","doi":"https://doi.org/10.1109/iscas.2019.8701882","mag":"2943784901"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2019.8701882","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2019.8701882","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020521295","display_name":"Imon Mondal","orcid":"https://orcid.org/0000-0002-7047-184X"},"institutions":[{"id":"https://openalex.org/I94234084","display_name":"Indian Institute of Technology Kanpur","ror":"https://ror.org/05pjsgx75","country_code":"IN","type":"education","lineage":["https://openalex.org/I94234084"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Imon Mondal","raw_affiliation_strings":["Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur, India","institution_ids":["https://openalex.org/I94234084"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5020521295"],"corresponding_institution_ids":["https://openalex.org/I94234084"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.05378883,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/group-delay-and-phase-delay","display_name":"Group delay and phase delay","score":0.599088728427887},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4889315664768219},{"id":"https://openalex.org/keywords/voltage-droop","display_name":"Voltage droop","score":0.4819614589214325},{"id":"https://openalex.org/keywords/wideband","display_name":"Wideband","score":0.47063112258911133},{"id":"https://openalex.org/keywords/low-pass-filter","display_name":"Low-pass filter","score":0.45900365710258484},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.4451519250869751},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.43975886702537537},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.43740054965019226},{"id":"https://openalex.org/keywords/transfer-function","display_name":"Transfer function","score":0.4202977418899536},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3590761423110962},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.34757107496261597},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.34318310022354126},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.26588571071624756},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13766983151435852},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1105455756187439}],"concepts":[{"id":"https://openalex.org/C123792056","wikidata":"https://www.wikidata.org/wiki/Q365988","display_name":"Group delay and phase delay","level":3,"score":0.599088728427887},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4889315664768219},{"id":"https://openalex.org/C40760162","wikidata":"https://www.wikidata.org/wiki/Q10920295","display_name":"Voltage droop","level":4,"score":0.4819614589214325},{"id":"https://openalex.org/C2780202535","wikidata":"https://www.wikidata.org/wiki/Q4524457","display_name":"Wideband","level":2,"score":0.47063112258911133},{"id":"https://openalex.org/C44682112","wikidata":"https://www.wikidata.org/wiki/Q918242","display_name":"Low-pass filter","level":3,"score":0.45900365710258484},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.4451519250869751},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.43975886702537537},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.43740054965019226},{"id":"https://openalex.org/C81299745","wikidata":"https://www.wikidata.org/wiki/Q334269","display_name":"Transfer function","level":2,"score":0.4202977418899536},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3590761423110962},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.34757107496261597},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.34318310022354126},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.26588571071624756},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13766983151435852},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1105455756187439},{"id":"https://openalex.org/C49324399","wikidata":"https://www.wikidata.org/wiki/Q466758","display_name":"Voltage divider","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2019.8701882","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2019.8701882","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1513573663","https://openalex.org/W1575583166","https://openalex.org/W1607069949","https://openalex.org/W2017013043","https://openalex.org/W2121226030","https://openalex.org/W2159842051","https://openalex.org/W2171846997","https://openalex.org/W2618546898","https://openalex.org/W3146238732","https://openalex.org/W6630655209"],"related_works":["https://openalex.org/W2523432015","https://openalex.org/W2765340260","https://openalex.org/W2014539368","https://openalex.org/W2115559056","https://openalex.org/W2166184725","https://openalex.org/W1901226250","https://openalex.org/W2098321236","https://openalex.org/W2147572790","https://openalex.org/W2256959580","https://openalex.org/W2790272948"],"abstract_inverted_index":{"Integrated":[0],"circuit":[1],"(IC)":[2],"active":[3],"all-pass":[4,67],"filters":[5],"with":[6],"(almost)":[7],"linear":[8],"phase":[9],"can":[10],"provide":[11],"large,":[12],"wideband":[13],"delays":[14],"while":[15],"consuming":[16],"small":[17],"chip":[18],"area,":[19],"and":[20,46,93,124],"offer":[21],"an":[22,51,56],"alternative":[23],"to":[24],"the":[25,44,59,66,78,83,86,90,95,101,104,120,125,133,136,140],"bulky":[26],"passive":[27],"element":[28],"based":[29],"delay":[30,97,116,141],"lines.":[31],"However,":[32],"they":[33],"suffer":[34],"from":[35],"transconductor":[36],"non-idealities":[37],"like":[38],"non-zero":[39],"output":[40,80],"conductance,":[41],"mismatch":[42],"between":[43,100],"transconductors,":[45],"non-negligible":[47],"interconnect":[48,127],"resistances":[49,128],"in":[50,107],"IC.":[52],"This":[53],"paper":[54],"presents":[55],"analysis":[57],"of":[58,61,63,82,89,135],"effect":[60],"each":[62],"these,":[64],"on":[65],"filter's":[68],"transfer":[69],"function.":[70],"It":[71],"is":[72],"shown":[73],"that":[74],"under":[75],"certain":[76],"conditions,":[77],"large":[79],"conductance":[81],"transconductors":[84,102],"reduces":[85],"in-band":[87],"gain":[88],"filter":[91,113,137],"uniformly":[92],"leaves":[94,119],"group":[96,115],"unaffected.":[98],"Mismatch":[99],"forming":[103],"LC":[105],"ladder":[106],"a":[108],"higher":[109],"order":[110],"singly":[111],"terminated":[112],"causes":[114],"fluctuations":[117],"but":[118],"magnitude":[121,130],"response":[122,142],"unaffected,":[123],"finite":[126],"introduce":[129],"droop":[131],"at":[132],"band-edge":[134],"without":[138],"affecting":[139],"significantly.":[143]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}