{"id":"https://openalex.org/W2801790922","doi":"https://doi.org/10.1109/iscas.2018.8351893","title":"Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes","display_name":"Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes","publication_year":2018,"publication_date":"2018-01-01","ids":{"openalex":"https://openalex.org/W2801790922","doi":"https://doi.org/10.1109/iscas.2018.8351893","mag":"2801790922"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2018.8351893","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2018.8351893","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://hdl.handle.net/11380/1328057","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051779027","display_name":"Martino Dazzi","orcid":"https://orcid.org/0000-0002-4184-2170"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Martino Dazzi","raw_affiliation_strings":["DEI, University of Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DEI, University of Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033037232","display_name":"Pierpaolo Palestri","orcid":"https://orcid.org/0000-0002-1672-1166"},"institutions":[{"id":"https://openalex.org/I129043915","display_name":"University of Udine","ror":"https://ror.org/05ht0mh31","country_code":"IT","type":"education","lineage":["https://openalex.org/I129043915"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Pierpaolo Palestri","raw_affiliation_strings":["DPIA, University of Udine, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DPIA, University of Udine, Italy","institution_ids":["https://openalex.org/I129043915"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023905268","display_name":"Davide Rossi","orcid":"https://orcid.org/0000-0002-0651-5393"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Davide Rossi","raw_affiliation_strings":["DEI, University of Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DEI, University of Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060798247","display_name":"Andrea Bandiziol","orcid":"https://orcid.org/0000-0002-7950-0416"},"institutions":[{"id":"https://openalex.org/I129043915","display_name":"University of Udine","ror":"https://ror.org/05ht0mh31","country_code":"IT","type":"education","lineage":["https://openalex.org/I129043915"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Andrea Bandiziol","raw_affiliation_strings":["DPIA, University of Udine, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DPIA, University of Udine, Italy","institution_ids":["https://openalex.org/I129043915"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046255006","display_name":"Igor Loi","orcid":"https://orcid.org/0000-0003-3852-4662"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Igor Loi","raw_affiliation_strings":["DEI, University of Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DEI, University of Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038237473","display_name":"David E. Bellasi","orcid":"https://orcid.org/0000-0001-9295-1919"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"David Bellasi","raw_affiliation_strings":["Integrated System Laboratory ETH, Zuerich, Switzerland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated System Laboratory ETH, Zuerich, Switzerland","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043408422","display_name":"Luca Benini","orcid":"https://orcid.org/0000-0001-8068-3806"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Luca Benini","raw_affiliation_strings":["Integrated System Laboratory ETH, Zuerich, Switzerland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated System Laboratory ETH, Zuerich, Switzerland","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.3379,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.87904348,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.7946474552154541},{"id":"https://openalex.org/keywords/transceiver","display_name":"Transceiver","score":0.6862051486968994},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.6603777408599854},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6188841462135315},{"id":"https://openalex.org/keywords/swing","display_name":"Swing","score":0.4601178467273712},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.45241355895996094},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43482735753059387},{"id":"https://openalex.org/keywords/clock-recovery","display_name":"Clock recovery","score":0.4262884855270386},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3642367720603943},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3577243983745575},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.33314719796180725},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.2927340865135193},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22752782702445984},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.21074125170707703},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.20254021883010864}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.7946474552154541},{"id":"https://openalex.org/C7720470","wikidata":"https://www.wikidata.org/wiki/Q954187","display_name":"Transceiver","level":3,"score":0.6862051486968994},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.6603777408599854},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6188841462135315},{"id":"https://openalex.org/C65655974","wikidata":"https://www.wikidata.org/wiki/Q14867674","display_name":"Swing","level":2,"score":0.4601178467273712},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.45241355895996094},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43482735753059387},{"id":"https://openalex.org/C2779835379","wikidata":"https://www.wikidata.org/wiki/Q2348121","display_name":"Clock recovery","level":4,"score":0.4262884855270386},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3642367720603943},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3577243983745575},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.33314719796180725},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.2927340865135193},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22752782702445984},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.21074125170707703},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.20254021883010864},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/iscas.2018.8351893","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2018.8351893","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},{"id":"pmh:oai:air.uniud.it:11390/1135441","is_oa":false,"landing_page_url":"http://hdl.handle.net/11390/1135441","pdf_url":null,"source":{"id":"https://openalex.org/S4306401163","display_name":"Institutional Research Information System (University of Udine)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I129043915","host_organization_name":"University of Udine","host_organization_lineage":["https://openalex.org/I129043915"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:cris.unibo.it:11585/653374","is_oa":false,"landing_page_url":"http://hdl.handle.net/11585/653374","pdf_url":null,"source":{"id":"https://openalex.org/S4306402579","display_name":"Archivio istituzionale della ricerca (Alma Mater Studiorum Universit\u00e0 di Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210117483","host_organization_name":"Istituto di Ematologia di Bologna","host_organization_lineage":["https://openalex.org/I4210117483"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:iris.unimore.it:11380/1328057","is_oa":true,"landing_page_url":"https://hdl.handle.net/11380/1328057","pdf_url":null,"source":{"id":"https://openalex.org/S4306400718","display_name":"IRIS UNIMORE (University of Modena and Reggio Emilia)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I122346577","host_organization_name":"University of Modena and Reggio Emilia","host_organization_lineage":["https://openalex.org/I122346577"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:iris.unimore.it:11380/1328057","is_oa":true,"landing_page_url":"https://hdl.handle.net/11380/1328057","pdf_url":null,"source":{"id":"https://openalex.org/S4306400718","display_name":"IRIS UNIMORE (University of Modena and Reggio Emilia)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I122346577","host_organization_name":"University of Modena and Reggio Emilia","host_organization_lineage":["https://openalex.org/I122346577"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"},"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8799999952316284,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1520631570","https://openalex.org/W1850497187","https://openalex.org/W1968541012","https://openalex.org/W1968632892","https://openalex.org/W1981474079","https://openalex.org/W2023225805","https://openalex.org/W2075259600","https://openalex.org/W2075883398","https://openalex.org/W2098969636","https://openalex.org/W2115198382","https://openalex.org/W2140916121","https://openalex.org/W2172040238","https://openalex.org/W2173515608","https://openalex.org/W2181798177","https://openalex.org/W2246694976","https://openalex.org/W2557387230","https://openalex.org/W2601028978","https://openalex.org/W2627706518","https://openalex.org/W2756825072","https://openalex.org/W2763302904"],"related_works":["https://openalex.org/W1565428738","https://openalex.org/W2113302467","https://openalex.org/W2181640182","https://openalex.org/W2554461666","https://openalex.org/W3083817078","https://openalex.org/W2755363281","https://openalex.org/W1976203537","https://openalex.org/W2144347227","https://openalex.org/W2612287248","https://openalex.org/W2154966820"],"abstract_inverted_index":{"We":[0],"report":[1],"on":[2],"the":[3,6,89,92],"design":[4],"of":[5,9,55,91,99],"physical":[7],"layer":[8],"a":[10,52,84],"high-speed":[11],"serial":[12],"interface":[13],"for":[14,62],"chip-to-chip":[15],"communication,":[16],"targeting":[17],"low":[18],"cost":[19],"and":[20,58,65,97],"ultra-low":[21],"power":[22,98],"(mW)":[23],"IoT":[24],"end-nodes.":[25],"Two":[26],"differential":[27],"lanes":[28],"(one":[29],"pair":[30],"per":[31],"direction)":[32],"are":[33],"used":[34],"to":[35,51,73],"transmit/receive":[36],"NRZ":[37],"symbols":[38],"at":[39],"1Gpbs":[40],"with":[41,83,88],"embedded":[42],"clock.":[43],"The":[44,69],"energy-per-bit":[45],"is":[46,71],"lower":[47],"than":[48],"1pJ/bit,":[49],"thanks":[50],"careful":[53],"selection":[54],"termination":[56],"impedance":[57],"voltage":[59],"swing,":[60],"tuned":[61],"moderate":[63],"speed":[64],"short":[66],"distance":[67],"(2cm).":[68],"transceiver":[70],"designed":[72],"tolerate":[74],"significant":[75],"clock":[76,86],"jitter,":[77],"so":[78],"that":[79],"it":[80],"can":[81],"work":[82],"half-rate":[85],"shared":[87],"rest":[90],"chip,":[93],"thereby":[94],"minimizing":[95],"area":[96],"supporting":[100],"circuitry.":[101]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
