{"id":"https://openalex.org/W2800111511","doi":"https://doi.org/10.1109/iscas.2018.8351798","title":"Comparison of Recently Developed Single-Bit All-Digital Frequency Synthesizers in Terms of Hardware Complexity and Performance","display_name":"Comparison of Recently Developed Single-Bit All-Digital Frequency Synthesizers in Terms of Hardware Complexity and Performance","publication_year":2018,"publication_date":"2018-01-01","ids":{"openalex":"https://openalex.org/W2800111511","doi":"https://doi.org/10.1109/iscas.2018.8351798","mag":"2800111511"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2018.8351798","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2018.8351798","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5009628361","display_name":"Charis Basetas","orcid":null},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"Charis Basetas","raw_affiliation_strings":["Department of Electrical and Computer Engineering, National Technical University of Athens, Greece"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, National Technical University of Athens, Greece","institution_ids":["https://openalex.org/I174458059"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030451270","display_name":"Nikos Temenos","orcid":"https://orcid.org/0000-0002-1763-9930"},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Nikos Temenos","raw_affiliation_strings":["Department of Electrical and Computer Engineering, National Technical University of Athens, Greece"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, National Technical University of Athens, Greece","institution_ids":["https://openalex.org/I174458059"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013213336","display_name":"Paul P. Sotiriadis","orcid":"https://orcid.org/0000-0001-6030-4645"},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Paul P. Sotiriadis","raw_affiliation_strings":["Department of Electrical and Computer Engineering, National Technical University of Athens, Greece"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, National Technical University of Athens, Greece","institution_ids":["https://openalex.org/I174458059"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5009628361"],"corresponding_institution_ids":["https://openalex.org/I174458059"],"apc_list":null,"apc_paid":null,"fwci":0.2575,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.55326693,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"13","issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.768984317779541},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6931285858154297},{"id":"https://openalex.org/keywords/transceiver","display_name":"Transceiver","score":0.6757050156593323},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4951144754886627},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4520546793937683},{"id":"https://openalex.org/keywords/qam","display_name":"QAM","score":0.435332715511322},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.43433642387390137},{"id":"https://openalex.org/keywords/delta-sigma-modulation","display_name":"Delta-sigma modulation","score":0.4226621985435486},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.40487825870513916},{"id":"https://openalex.org/keywords/quadrature-amplitude-modulation","display_name":"Quadrature amplitude modulation","score":0.38516664505004883},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.22641026973724365},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.19766351580619812},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.17989706993103027},{"id":"https://openalex.org/keywords/bit-error-rate","display_name":"Bit error rate","score":0.1584315001964569},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10253721475601196}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.768984317779541},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6931285858154297},{"id":"https://openalex.org/C7720470","wikidata":"https://www.wikidata.org/wiki/Q954187","display_name":"Transceiver","level":3,"score":0.6757050156593323},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4951144754886627},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4520546793937683},{"id":"https://openalex.org/C59030546","wikidata":"https://www.wikidata.org/wiki/Q7265371","display_name":"QAM","level":5,"score":0.435332715511322},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.43433642387390137},{"id":"https://openalex.org/C68754193","wikidata":"https://www.wikidata.org/wiki/Q1184820","display_name":"Delta-sigma modulation","level":3,"score":0.4226621985435486},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.40487825870513916},{"id":"https://openalex.org/C32409245","wikidata":"https://www.wikidata.org/wiki/Q749753","display_name":"Quadrature amplitude modulation","level":4,"score":0.38516664505004883},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.22641026973724365},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.19766351580619812},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.17989706993103027},{"id":"https://openalex.org/C56296756","wikidata":"https://www.wikidata.org/wiki/Q840922","display_name":"Bit error rate","level":3,"score":0.1584315001964569},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10253721475601196}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2018.8351798","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2018.8351798","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5299999713897705,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W605564925","https://openalex.org/W2142918534","https://openalex.org/W2151384663","https://openalex.org/W2162755111","https://openalex.org/W2469724083","https://openalex.org/W2478884216","https://openalex.org/W2529231278","https://openalex.org/W2542943525","https://openalex.org/W2553412645","https://openalex.org/W2765239936","https://openalex.org/W2765387923","https://openalex.org/W2766858126","https://openalex.org/W2891646015","https://openalex.org/W4301627548","https://openalex.org/W6745479675","https://openalex.org/W6745537146"],"related_works":["https://openalex.org/W4390873927","https://openalex.org/W2159438609","https://openalex.org/W2900995485","https://openalex.org/W2147334234","https://openalex.org/W3196902411","https://openalex.org/W2139936226","https://openalex.org/W1970526599","https://openalex.org/W2064534496","https://openalex.org/W3026565890","https://openalex.org/W2161389097"],"abstract_inverted_index":{"Internet":[0,32],"of":[1,7,33,55,66,75],"Things":[2,34],"growth":[3],"requires":[4],"the":[5,56,94,97],"development":[6],"low":[8,11],"power":[9],"and":[10,49,71,78],"cost":[12],"wireless":[13],"transceivers.":[14],"Here,":[15],"we":[16],"present":[17],"three":[18,57],"recently":[19],"developed":[20],"all-digital":[21,37],"frequency":[22],"synthesizer":[23],"architectures":[24,59,68],"which":[25],"can":[26],"be":[27],"used":[28],"as":[29],"transmitters":[30,38],"for":[31,101],"applications.":[35],"These":[36],"are":[39,60,69,90],"based":[40],"on":[41],"different":[42],"sigma-delta":[43],"modulator":[44],"architectures,":[45],"varying":[46],"in":[47,73],"performance":[48,81],"hardware":[50,76],"complexity.":[51],"The":[52],"operation":[53],"principles":[54],"proposed":[58],"described.":[61],"Then,":[62],"proof-of-concept":[63],"FPGA":[64],"implementations":[65],"these":[67],"presented":[70],"compared":[72],"terms":[74],"resources":[77],"speed.":[79],"Their":[80],"is":[82],"tested":[83],"using":[84],"32-QAM":[85],"modulated":[86],"signals.":[87],"Finally,":[88],"conclusions":[89],"drawn":[91],"to":[92],"help":[93],"reader":[95],"select":[96],"most":[98],"suitable":[99],"architecture":[100],"a":[102],"given":[103],"application.":[104]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
