{"id":"https://openalex.org/W2802617484","doi":"https://doi.org/10.1109/iscas.2018.8351565","title":"Description of SAR ADCs with Digital Redundancy using a Unified Hardware-Based Approach","display_name":"Description of SAR ADCs with Digital Redundancy using a Unified Hardware-Based Approach","publication_year":2018,"publication_date":"2018-01-01","ids":{"openalex":"https://openalex.org/W2802617484","doi":"https://doi.org/10.1109/iscas.2018.8351565","mag":"2802617484"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2018.8351565","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2018.8351565","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072282417","display_name":"Antonio Gin\u00e9s","orcid":"https://orcid.org/0000-0001-5272-5802"},"institutions":[{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]},{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Antonio Gines","raw_affiliation_strings":["Instituto de Microelectr\u00f3nica de Sevilla IMSE-CNM (CSIC - Universidad de Sevilla), Seville, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Microelectr\u00f3nica de Sevilla IMSE-CNM (CSIC - Universidad de Sevilla), Seville, Spain","institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078655536","display_name":"Antonio Lopez-Angulo","orcid":"https://orcid.org/0000-0002-4548-3638"},"institutions":[{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]},{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Antonio Lopez-Angulo","raw_affiliation_strings":["Instituto de Microelectr\u00f3nica de Sevilla IMSE-CNM (CSIC - Universidad de Sevilla), Seville, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Microelectr\u00f3nica de Sevilla IMSE-CNM (CSIC - Universidad de Sevilla), Seville, Spain","institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091600572","display_name":"E. Peral\u00edas","orcid":"https://orcid.org/0000-0003-0629-0785"},"institutions":[{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]},{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Eduardo Peralias","raw_affiliation_strings":["Instituto de Microelectr\u00f3nica de Sevilla IMSE-CNM (CSIC - Universidad de Sevilla), Seville, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Microelectr\u00f3nica de Sevilla IMSE-CNM (CSIC - Universidad de Sevilla), Seville, Spain","institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5066990447","display_name":"A. Rueda","orcid":"https://orcid.org/0000-0003-4564-9359"},"institutions":[{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]},{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Adoracion Rueda","raw_affiliation_strings":["Instituto de Microelectr\u00f3nica de Sevilla IMSE-CNM (CSIC - Universidad de Sevilla), Seville, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Microelectr\u00f3nica de Sevilla IMSE-CNM (CSIC - Universidad de Sevilla), Seville, Spain","institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.5917,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.88512151,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"3003","issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.8506219387054443},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6838164925575256},{"id":"https://openalex.org/keywords/comparator","display_name":"Comparator","score":0.5901396870613098},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.520733118057251},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4594796895980835},{"id":"https://openalex.org/keywords/successive-approximation-adc","display_name":"Successive approximation ADC","score":0.4378495514392853},{"id":"https://openalex.org/keywords/binary-number","display_name":"Binary number","score":0.4365927278995514},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3895975947380066},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3737238049507141},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36198365688323975},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.19093286991119385},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16782739758491516},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11460313200950623},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.11060634255409241},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10680520534515381}],"concepts":[{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.8506219387054443},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6838164925575256},{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.5901396870613098},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.520733118057251},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4594796895980835},{"id":"https://openalex.org/C60154766","wikidata":"https://www.wikidata.org/wiki/Q2650458","display_name":"Successive approximation ADC","level":4,"score":0.4378495514392853},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.4365927278995514},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3895975947380066},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3737238049507141},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36198365688323975},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.19093286991119385},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16782739758491516},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11460313200950623},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.11060634255409241},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10680520534515381},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2018.8351565","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2018.8351565","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1528298974","https://openalex.org/W1584667699","https://openalex.org/W1964531905","https://openalex.org/W1974931639","https://openalex.org/W2053451635","https://openalex.org/W2101004723","https://openalex.org/W2102581641","https://openalex.org/W2104359526","https://openalex.org/W2107169806","https://openalex.org/W2111186324","https://openalex.org/W2151398553","https://openalex.org/W2167161290","https://openalex.org/W2171146006","https://openalex.org/W2535745143","https://openalex.org/W2564345649","https://openalex.org/W6675157575"],"related_works":["https://openalex.org/W2278942241","https://openalex.org/W2368405386","https://openalex.org/W1977749038","https://openalex.org/W2082979872","https://openalex.org/W1641489184","https://openalex.org/W3004044036","https://openalex.org/W2792167570","https://openalex.org/W2290076986","https://openalex.org/W4312326809","https://openalex.org/W2039630794"],"abstract_inverted_index":{"This":[0],"paper":[1],"analyzes":[2],"the":[3,28,37,71,75,96],"state-of-the-art":[4],"in":[5,36,70],"Successive-Approximation-Register":[6],"(SAR)":[7],"ADCs":[8],"with":[9,24,83],"digital":[10],"redundancy":[11,40],"using":[12,95],"a":[13,58],"unified":[14],"nomenclature":[15],"and":[16,51,61,86,93],"modeling.":[17],"Redundancy":[18],"provides":[19],"tolerance":[20],"intervals":[21],"for":[22,64],"dealing":[23],"comparison":[25],"errors":[26],"during":[27],"SAR":[29],"search":[30],"algorithm":[31],"due":[32],"to":[33],"incomplete":[34],"settling":[35],"DAC.":[38],"Employing":[39],"improves":[41],"conversion":[42],"speed/power":[43],"trade-off":[44],"as":[45,47],"well":[46],"relaxes":[48],"switch":[49],"sizes":[50],"comparator":[52],"design.":[53],"The":[54],"proposed":[55,97],"description":[56],"presents":[57],"common":[59],"theoretical":[60],"physical":[62],"framework":[63],"analyzing":[65],"existing":[66],"(apparently":[67],"different)":[68],"techniques":[69],"bibliography,":[72],"independently":[73],"of":[74],"practical":[76],"realization":[77],"(binary":[78],"or":[79],"arbitrary":[80],"scaled":[81],"capacitors":[82],"redundant":[84],"bits)":[85],"switching":[87],"schemes.":[88],"Several":[89],"examples":[90],"are":[91],"modeled":[92],"simulated":[94],"approach.":[98]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
