{"id":"https://openalex.org/W2800869073","doi":"https://doi.org/10.1109/iscas.2018.8351560","title":"Fast Performance Evaluation for Analog Circuit Synthesis Frameworks","display_name":"Fast Performance Evaluation for Analog Circuit Synthesis Frameworks","publication_year":2018,"publication_date":"2018-05-01","ids":{"openalex":"https://openalex.org/W2800869073","doi":"https://doi.org/10.1109/iscas.2018.8351560","mag":"2800869073"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2018.8351560","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2018.8351560","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059244271","display_name":"Zhenxin Zhao","orcid":"https://orcid.org/0000-0003-4902-353X"},"institutions":[{"id":"https://openalex.org/I130438778","display_name":"Memorial University of Newfoundland","ror":"https://ror.org/04haebc03","country_code":"CA","type":"education","lineage":["https://openalex.org/I130438778"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Zhenxin Zhao","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Memorial University of Newfoundland, St. John's, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Memorial University of Newfoundland, St. John's, Canada","institution_ids":["https://openalex.org/I130438778"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009347758","display_name":"Tuotian Liao","orcid":"https://orcid.org/0000-0003-0294-6804"},"institutions":[{"id":"https://openalex.org/I130438778","display_name":"Memorial University of Newfoundland","ror":"https://ror.org/04haebc03","country_code":"CA","type":"education","lineage":["https://openalex.org/I130438778"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Tuotian Liao","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Memorial University of Newfoundland, St. John's, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Memorial University of Newfoundland, St. John's, Canada","institution_ids":["https://openalex.org/I130438778"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100705837","display_name":"Lihong Zhang","orcid":"https://orcid.org/0000-0003-2946-8072"},"institutions":[{"id":"https://openalex.org/I130438778","display_name":"Memorial University of Newfoundland","ror":"https://ror.org/04haebc03","country_code":"CA","type":"education","lineage":["https://openalex.org/I130438778"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Lihong Zhang","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Memorial University of Newfoundland, St. John's, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Memorial University of Newfoundland, St. John's, Canada","institution_ids":["https://openalex.org/I130438778"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I130438778"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9952999949455261,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6941046714782715},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.6594839692115784},{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.5720757246017456},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.4570373296737671},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.4207564890384674},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.393931120634079},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.375510573387146},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3716409206390381},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.32077497243881226},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.2882590591907501},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.22649696469306946},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11719733476638794},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.09405741095542908}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6941046714782715},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.6594839692115784},{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.5720757246017456},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.4570373296737671},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.4207564890384674},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.393931120634079},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.375510573387146},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3716409206390381},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.32077497243881226},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.2882590591907501},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.22649696469306946},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11719733476638794},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.09405741095542908},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2018.8351560","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2018.8351560","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.47999998927116394,"display_name":"Partnerships for the goals","id":"https://metadata.un.org/sdg/17"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W22126472","https://openalex.org/W2018790177","https://openalex.org/W2034498767","https://openalex.org/W2044500638","https://openalex.org/W2046328375","https://openalex.org/W2129159815","https://openalex.org/W2131602584","https://openalex.org/W2152293425","https://openalex.org/W2539776105","https://openalex.org/W2595409684","https://openalex.org/W4255048693","https://openalex.org/W6600849004","https://openalex.org/W6679472356","https://openalex.org/W6682627371"],"related_works":["https://openalex.org/W3154683910","https://openalex.org/W1846734616","https://openalex.org/W2359532622","https://openalex.org/W3134543635","https://openalex.org/W2921318524","https://openalex.org/W2377571686","https://openalex.org/W4380988671","https://openalex.org/W2375192119","https://openalex.org/W2122222688","https://openalex.org/W1933057227"],"abstract_inverted_index":{"Evaluating":[0],"the":[1,13,60,65,85,94,104,111],"performance":[2,40],"of":[3,38,87,103,121],"schematic-level":[4],"un-sized":[5,88],"circuits":[6],"is":[7],"always":[8],"a":[9,35,118],"challenging":[10],"task":[11],"within":[12],"automated":[14],"analog":[15,48],"circuit":[16,49,89,113,122],"synthesis":[17,50,114],"process.":[18],"One":[19],"has":[20],"to":[21,28,46,54,83,93],"trade":[22],"accuracy":[23],"for":[24,124],"efficiency":[25],"in":[26],"order":[27],"maintain":[29],"efficient":[30],"synthesis.":[31],"This":[32],"paper":[33],"presents":[34],"new":[36],"method":[37],"fast":[39],"evaluation,":[41],"which":[42],"can":[43,108],"be":[44],"applied":[45],"general":[47],"frameworks.":[51],"We":[52],"propose":[53],"integrate":[55],"graph-based":[56],"symbolic":[57],"analysis":[58],"with":[59,91],"curve-fitting":[61],"technique":[62],"by":[63,116],"using":[64],"g":[66],"<sub":[67,71],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[68,72],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">m</sub>":[69],"/l":[70],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">D</sub>":[73],"methodology.":[74],"Both":[75],"linear":[76],"programming":[77,80],"and":[78,127],"nonlinear":[79],"are":[81],"utilized":[82],"validate":[84],"feasibility":[86],"topology":[90],"reference":[92],"defined":[95],"specifications.":[96],"Our":[97],"experimental":[98],"results":[99],"indicate":[100],"high":[101],"efficacy":[102],"proposed":[105],"method.":[106],"It":[107],"significantly":[109],"reduce":[110],"entire":[112],"time":[115],"leaving":[117],"small":[119],"number":[120],"topologies":[123],"detailed":[125],"sizing":[126],"further":[128],"evaluation.":[129]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":7},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":4}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}