{"id":"https://openalex.org/W2802208391","doi":"https://doi.org/10.1109/iscas.2018.8351503","title":"Area-effcient re-encoding scheme for NAND Flash Memory with multimode BCH Error correction","display_name":"Area-effcient re-encoding scheme for NAND Flash Memory with multimode BCH Error correction","publication_year":2018,"publication_date":"2018-01-01","ids":{"openalex":"https://openalex.org/W2802208391","doi":"https://doi.org/10.1109/iscas.2018.8351503","mag":"2802208391"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2018.8351503","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2018.8351503","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066089541","display_name":"Arul K. Subbiah","orcid":"https://orcid.org/0000-0003-1276-5193"},"institutions":[{"id":"https://openalex.org/I16269868","display_name":"Santa Clara University","ror":"https://ror.org/03ypqe447","country_code":"US","type":"education","lineage":["https://openalex.org/I16269868"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Arul K. Subbiah","raw_affiliation_strings":["Department of Electrical Engineering, Santa Clara University, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Santa Clara University, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I16269868"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025538938","display_name":"Tokunbo Ogunfunmi","orcid":"https://orcid.org/0000-0003-3517-9779"},"institutions":[{"id":"https://openalex.org/I16269868","display_name":"Santa Clara University","ror":"https://ror.org/03ypqe447","country_code":"US","type":"education","lineage":["https://openalex.org/I16269868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tokunbo Ogunfunmi","raw_affiliation_strings":["Department of Electrical Engineering, Santa Clara University, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Santa Clara University, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I16269868"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5066089541"],"corresponding_institution_ids":["https://openalex.org/I16269868"],"apc_list":null,"apc_paid":null,"fwci":0.5536,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.69164973,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12162","display_name":"Cellular Automata and Applications","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.986299991607666,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/bch-code","display_name":"BCH code","score":0.9804883599281311},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7489290833473206},{"id":"https://openalex.org/keywords/encoder","display_name":"Encoder","score":0.6770729422569275},{"id":"https://openalex.org/keywords/encoding","display_name":"Encoding (memory)","score":0.55096435546875},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.5039247870445251},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.4961608350276947},{"id":"https://openalex.org/keywords/shift-register","display_name":"Shift register","score":0.47208330035209656},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4572888910770416},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.40095803141593933},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3333357572555542},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.17548081278800964},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08729532361030579}],"concepts":[{"id":"https://openalex.org/C42276685","wikidata":"https://www.wikidata.org/wiki/Q795705","display_name":"BCH code","level":3,"score":0.9804883599281311},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7489290833473206},{"id":"https://openalex.org/C118505674","wikidata":"https://www.wikidata.org/wiki/Q42586063","display_name":"Encoder","level":2,"score":0.6770729422569275},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.55096435546875},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.5039247870445251},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.4961608350276947},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.47208330035209656},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4572888910770416},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.40095803141593933},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3333357572555542},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.17548081278800964},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08729532361030579},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2018.8351503","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2018.8351503","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1450066936","https://openalex.org/W1534925464","https://openalex.org/W1569071776","https://openalex.org/W1980308149","https://openalex.org/W2036930611","https://openalex.org/W2109236154","https://openalex.org/W2135671115","https://openalex.org/W2139910577","https://openalex.org/W2293516228","https://openalex.org/W2602222563","https://openalex.org/W4239889878"],"related_works":["https://openalex.org/W2358290231","https://openalex.org/W1950940422","https://openalex.org/W4283822356","https://openalex.org/W3172524400","https://openalex.org/W1723747798","https://openalex.org/W2129146436","https://openalex.org/W2032507829","https://openalex.org/W2121197955","https://openalex.org/W2313229959","https://openalex.org/W2147282173"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,20,132],"novel":[4],"method":[5,76,130],"to":[6,37,62],"reduce":[7,63],"the":[8,11,47,64,73,78,83,87,90,95,99,108,122,125,129],"area":[9,39],"of":[10,98,110,119],"Bose":[12],"Chaudhuri":[13],"Hocquenghen":[14],"(BCH)":[15],"multimode":[16,26],"encoder":[17,88,123],"based":[18],"on":[19],"re-encoding":[21],"scheme.":[22],"Previous":[23],"methods":[24],"for":[25,43,53,67,86],"BCH":[27,45,69,100,111],"use":[28],"several":[29],"linear-feedback":[30],"shift":[31],"registers":[32],"(LFSR)":[33],"cascaded":[34],"in":[35,107],"series":[36],"achieve":[38],"efficient":[40],"encoder,":[41],"but":[42],"longer":[44],"codes":[46],"critical":[48,65],"path":[49,66],"becomes":[50],"an":[51],"issue":[52],"high":[54],"throughput.":[55],"A":[56],"new":[57],"encoding":[58],"scheme":[59],"is":[60,94],"proposed":[61],"long":[68],"code.":[70],"Without":[71],"sacrificing":[72],"latency,":[74],"this":[75],"reduces":[77],"hardware":[79],"complexity":[80],"by":[81],"reusing":[82],"same":[84],"module":[85],"and":[89,124,128],"syndrome":[91,126],"generator,":[92,127],"which":[93],"first":[96],"stage":[97],"decoder.":[101],"The":[102],"experimental":[103],"results":[104],"show":[105],"that,":[106],"case":[109],"(8191,":[112],"7983,":[113],"16),":[114],"there":[115],"are":[116],"logic":[117],"savings":[118],"25%":[120],"between":[121],"provides":[131],"reconfigurable":[133],"error":[134],"correction":[135],"capability":[136],"(tsel).":[137]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}