{"id":"https://openalex.org/W2802897963","doi":"https://doi.org/10.1109/iscas.2018.8351459","title":"Optimizing an Analog Neuron Circuit Design for Nonlinear Function Approximation","display_name":"Optimizing an Analog Neuron Circuit Design for Nonlinear Function Approximation","publication_year":2018,"publication_date":"2018-05-01","ids":{"openalex":"https://openalex.org/W2802897963","doi":"https://doi.org/10.1109/iscas.2018.8351459","mag":"2802897963"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2018.8351459","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2018.8351459","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074343619","display_name":"Alexander Neckar","orcid":"https://orcid.org/0000-0001-7225-3144"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Alexander Neckar","raw_affiliation_strings":["Electrical Engineering, Stanford University, Stanford, CA, U.S.A"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering, Stanford University, Stanford, CA, U.S.A","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069590039","display_name":"Terrence C. Stewart","orcid":"https://orcid.org/0000-0002-1445-7613"},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Terrence C. Stewart","raw_affiliation_strings":["Centre for Theoretical Neuroscience, University of Waterloo, Waterloo, ON, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Centre for Theoretical Neuroscience, University of Waterloo, Waterloo, ON, Canada","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060326828","display_name":"Ben Varkey Benjamin","orcid":"https://orcid.org/0000-0002-6840-7136"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ben V. Benjamin","raw_affiliation_strings":["Electrical Engineering, Stanford University, Stanford, CA, U.S.A"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering, Stanford University, Stanford, CA, U.S.A","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077089453","display_name":"Kwabena Boahen","orcid":"https://orcid.org/0000-0003-2301-3309"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kwabena Boahen","raw_affiliation_strings":["Bioengineering and Electrical Engineering, Stanford University, Stanford, CA, U.S.A"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Bioengineering and Electrical Engineering, Stanford University, Stanford, CA, U.S.A","institution_ids":["https://openalex.org/I97018004"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.3379,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.87927779,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"1","issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/subthreshold-conduction","display_name":"Subthreshold conduction","score":0.7485835552215576},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5690062046051025},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5666415691375732},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5565803647041321},{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.542422354221344},{"id":"https://openalex.org/keywords/nonlinear-system","display_name":"Nonlinear system","score":0.47567787766456604},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4480944275856018},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.4219200015068054},{"id":"https://openalex.org/keywords/threshold-voltage","display_name":"Threshold voltage","score":0.4145289361476898},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3822673261165619},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.34113866090774536},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3048868775367737},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.25784391164779663},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.17738282680511475},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14411014318466187}],"concepts":[{"id":"https://openalex.org/C156465305","wikidata":"https://www.wikidata.org/wiki/Q1658601","display_name":"Subthreshold conduction","level":4,"score":0.7485835552215576},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5690062046051025},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5666415691375732},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5565803647041321},{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.542422354221344},{"id":"https://openalex.org/C158622935","wikidata":"https://www.wikidata.org/wiki/Q660848","display_name":"Nonlinear system","level":2,"score":0.47567787766456604},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4480944275856018},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.4219200015068054},{"id":"https://openalex.org/C195370968","wikidata":"https://www.wikidata.org/wiki/Q1754002","display_name":"Threshold voltage","level":4,"score":0.4145289361476898},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3822673261165619},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.34113866090774536},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3048868775367737},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.25784391164779663},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.17738282680511475},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14411014318466187},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2018.8351459","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2018.8351459","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.550000011920929,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320337345","display_name":"Office of Naval Research","ror":"https://ror.org/00rk2pe57"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W639309485","https://openalex.org/W1184351409","https://openalex.org/W1983278353","https://openalex.org/W2050461003","https://openalex.org/W2051385641","https://openalex.org/W2072024971","https://openalex.org/W2082734621","https://openalex.org/W2103452702","https://openalex.org/W2137609251","https://openalex.org/W2139988644","https://openalex.org/W2320696484","https://openalex.org/W2595593680","https://openalex.org/W2757810720","https://openalex.org/W2759596461","https://openalex.org/W2761564987","https://openalex.org/W4232444853","https://openalex.org/W6680302763","https://openalex.org/W6680464865","https://openalex.org/W6744996651"],"related_works":["https://openalex.org/W2806295079","https://openalex.org/W3100668214","https://openalex.org/W2009852498","https://openalex.org/W3004587385","https://openalex.org/W1991521745","https://openalex.org/W2109147260","https://openalex.org/W2786811717","https://openalex.org/W4220771873","https://openalex.org/W2069364674","https://openalex.org/W2062767191"],"abstract_inverted_index":{"Silicon":[0],"neurons":[1],"designed":[2],"using":[3],"subthreshold":[4],"analog-circuit":[5],"techniques":[6],"offer":[7],"low":[8],"power":[9],"and":[10],"compact":[11],"area":[12,115,159],"but":[13],"are":[14],"exponentially":[15],"sensitive":[16],"to":[17,49,62,68,128,147],"threshold-voltage":[18],"mismatch":[19,150],"in":[20,25,99,120,139],"transistors.":[21],"The":[22],"resulting":[23],"heterogeneity":[24],"the":[26,54,80,100,103],"neurons'":[27],"responses,":[28],"however,":[29],"provides":[30],"a":[31,108,123,140],"diverse":[32],"set":[33],"of":[34,102],"basis":[35],"functions":[36],"for":[37],"smooth":[38],"nonlinear":[39],"function":[40],"approximation.":[41],"For":[42],"low-order":[43],"polynomials,":[44],"neuron":[45],"spiking":[46],"thresholds":[47,77,96],"ought":[48],"be":[50],"distributed":[51],"uniformly":[52],"across":[53],"function's":[55],"domain.":[56,104],"This":[57],"uniform":[58],"distribution":[59],"is":[60],"difficult":[61],"achieve":[63],"solely":[64],"by":[65,116,160],"sizing":[66],"transistors":[67],"titrate":[69],"mismatch.":[70],"With":[71,90],"too":[72,91],"much":[73],"mismatch,":[74,93],"many":[75],"neuron's":[76,131],"fall":[78],"outside":[79],"domain":[81],"(i.e.":[82],"they":[83],"either":[84],"always":[85],"spike":[86],"or":[87],"remain":[88],"silent).":[89],"little":[92],"all":[94],"their":[95],"bunch":[97],"up":[98],"middle":[101],"Here,":[105],"we":[106],"present":[107],"silicon-neuron":[109],"design":[110],"methodology":[111,138],"that":[112],"minimizes":[113],"overall":[114],"optimizing":[117],"transistor":[118],"sizes":[119],"concert":[121],"with":[122,153],"few":[124],"locally-stored":[125],"programmable":[126],"bits":[127],"adjust":[129],"each":[130],"offset":[132],"(and":[133],"gain).":[134],"We":[135],"validated":[136],"this":[137],"28-nm":[141],"mixed":[142],"analog-digital":[143],"CMOS":[144],"process.":[145],"Compared":[146],"relying":[148],"on":[149],"alone,":[151],"augmentation":[152],"digital":[154],"correction":[155],"effectively":[156],"reduced":[157],"silicon":[158],"38%.":[161]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
