{"id":"https://openalex.org/W2802102201","doi":"https://doi.org/10.1109/iscas.2018.8351376","title":"An FPGA-Based Architecture of True Random Number Generator for Network Security Applications","display_name":"An FPGA-Based Architecture of True Random Number Generator for Network Security Applications","publication_year":2018,"publication_date":"2018-05-01","ids":{"openalex":"https://openalex.org/W2802102201","doi":"https://doi.org/10.1109/iscas.2018.8351376","mag":"2802102201"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2018.8351376","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2018.8351376","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006313189","display_name":"Guido Di Patrizio Stanchieri","orcid":"https://orcid.org/0000-0001-5279-6627"},"institutions":[{"id":"https://openalex.org/I26415053","display_name":"University of L'Aquila","ror":"https://ror.org/01j9p1r26","country_code":"IT","type":"education","lineage":["https://openalex.org/I26415053"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Guido Di Patrizio Stanchieri","raw_affiliation_strings":["Department of Industrial and Information Engineering and Economics, University of L\u2019 Aquila, L\u2019 Aquila, Italy","Department of Industrial and Information Engineering and Economics, University of L' Aquila, L' Aquila, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Industrial and Information Engineering and Economics, University of L\u2019 Aquila, L\u2019 Aquila, Italy","institution_ids":["https://openalex.org/I26415053"]},{"raw_affiliation_string":"Department of Industrial and Information Engineering and Economics, University of L' Aquila, L' Aquila, Italy","institution_ids":["https://openalex.org/I26415053"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071885582","display_name":"Andrea De Marcellis","orcid":"https://orcid.org/0000-0003-2490-7486"},"institutions":[{"id":"https://openalex.org/I26415053","display_name":"University of L'Aquila","ror":"https://ror.org/01j9p1r26","country_code":"IT","type":"education","lineage":["https://openalex.org/I26415053"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Andrea De Marcellis","raw_affiliation_strings":["Department of Industrial and Information Engineering and Economics, University of L\u2019 Aquila, L\u2019 Aquila, Italy","Department of Industrial and Information Engineering and Economics, University of L' Aquila, L' Aquila, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Industrial and Information Engineering and Economics, University of L\u2019 Aquila, L\u2019 Aquila, Italy","institution_ids":["https://openalex.org/I26415053"]},{"raw_affiliation_string":"Department of Industrial and Information Engineering and Economics, University of L' Aquila, L' Aquila, Italy","institution_ids":["https://openalex.org/I26415053"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008675649","display_name":"Marco Faccio","orcid":"https://orcid.org/0000-0002-2856-7733"},"institutions":[{"id":"https://openalex.org/I26415053","display_name":"University of L'Aquila","ror":"https://ror.org/01j9p1r26","country_code":"IT","type":"education","lineage":["https://openalex.org/I26415053"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Marco Faccio","raw_affiliation_strings":["Department of Industrial and Information Engineering and Economics, University of L\u2019 Aquila, L\u2019 Aquila, Italy","Department of Industrial and Information Engineering and Economics, University of L' Aquila, L' Aquila, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Industrial and Information Engineering and Economics, University of L\u2019 Aquila, L\u2019 Aquila, Italy","institution_ids":["https://openalex.org/I26415053"]},{"raw_affiliation_string":"Department of Industrial and Information Engineering and Economics, University of L' Aquila, L' Aquila, Italy","institution_ids":["https://openalex.org/I26415053"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026408860","display_name":"E. Palange","orcid":"https://orcid.org/0000-0002-2173-9985"},"institutions":[{"id":"https://openalex.org/I26415053","display_name":"University of L'Aquila","ror":"https://ror.org/01j9p1r26","country_code":"IT","type":"education","lineage":["https://openalex.org/I26415053"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Elia Palange","raw_affiliation_strings":["Department of Industrial and Information Engineering and Economics, University of L\u2019 Aquila, L\u2019 Aquila, Italy","Department of Industrial and Information Engineering and Economics, University of L' Aquila, L' Aquila, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Industrial and Information Engineering and Economics, University of L\u2019 Aquila, L\u2019 Aquila, Italy","institution_ids":["https://openalex.org/I26415053"]},{"raw_affiliation_string":"Department of Industrial and Information Engineering and Economics, University of L' Aquila, L' Aquila, Italy","institution_ids":["https://openalex.org/I26415053"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I26415053"],"apc_list":null,"apc_paid":null,"fwci":0.1521,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.48011227,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11017","display_name":"Chaos-based Image/Signal Encryption","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11017","display_name":"Chaos-based Image/Signal Encryption","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12162","display_name":"Cellular Automata and Applications","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9869999885559082,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8465538024902344},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.781815767288208},{"id":"https://openalex.org/keywords/bitstream","display_name":"Bitstream","score":0.7678883075714111},{"id":"https://openalex.org/keywords/random-number-generation","display_name":"Random number generation","score":0.7359123229980469},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.700401782989502},{"id":"https://openalex.org/keywords/nist","display_name":"NIST","score":0.6312793493270874},{"id":"https://openalex.org/keywords/ring-oscillator","display_name":"Ring oscillator","score":0.5368682742118835},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4758548438549042},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.4692041277885437},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.43081676959991455},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.4185764491558075},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4037245810031891},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.1758204996585846},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.14937293529510498},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1492384970188141},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10091736912727356}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8465538024902344},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.781815767288208},{"id":"https://openalex.org/C136695289","wikidata":"https://www.wikidata.org/wiki/Q415568","display_name":"Bitstream","level":3,"score":0.7678883075714111},{"id":"https://openalex.org/C201866948","wikidata":"https://www.wikidata.org/wiki/Q228206","display_name":"Random number generation","level":2,"score":0.7359123229980469},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.700401782989502},{"id":"https://openalex.org/C111219384","wikidata":"https://www.wikidata.org/wiki/Q6954384","display_name":"NIST","level":2,"score":0.6312793493270874},{"id":"https://openalex.org/C104111718","wikidata":"https://www.wikidata.org/wiki/Q2153973","display_name":"Ring oscillator","level":3,"score":0.5368682742118835},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4758548438549042},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.4692041277885437},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.43081676959991455},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.4185764491558075},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4037245810031891},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.1758204996585846},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.14937293529510498},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1492384970188141},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10091736912727356},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C204321447","wikidata":"https://www.wikidata.org/wiki/Q30642","display_name":"Natural language processing","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2018.8351376","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2018.8351376","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.6700000166893005,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W170084955","https://openalex.org/W1489565782","https://openalex.org/W1517403092","https://openalex.org/W1580991036","https://openalex.org/W1717406790","https://openalex.org/W1986590510","https://openalex.org/W2024414674","https://openalex.org/W2028424369","https://openalex.org/W2032644301","https://openalex.org/W2056526236","https://openalex.org/W2077721435","https://openalex.org/W2091221194","https://openalex.org/W2107217398","https://openalex.org/W2116948326","https://openalex.org/W2139280266","https://openalex.org/W2145430477","https://openalex.org/W2153122499","https://openalex.org/W2161890359","https://openalex.org/W2170141950","https://openalex.org/W2509263528","https://openalex.org/W2756617193","https://openalex.org/W2756627506","https://openalex.org/W2757205152"],"related_works":["https://openalex.org/W2910439186","https://openalex.org/W3134956345","https://openalex.org/W2773228113","https://openalex.org/W2523104764","https://openalex.org/W3004634482","https://openalex.org/W2922433876","https://openalex.org/W3084704944","https://openalex.org/W4381427530","https://openalex.org/W2610269622","https://openalex.org/W2054443616"],"abstract_inverted_index":{"This":[0],"paper":[1],"reports":[2],"on":[3,34,85],"a":[4,19,35,47,59,64,86,150],"True":[5],"Random":[6],"Number":[7],"Generator":[8],"(TRNG)":[9],"that":[10,66],"makes":[11],"use":[12,71],"of":[13,27,31,50,63,72,124,165],"the":[14,70,102,109,121,125,132,142,147,157,162,174,179],"period":[15],"jitter":[16],"introduced":[17],"by":[18,46,156],"Phase":[20],"Locked":[21],"Loop":[22],"(PLL)":[23],"used":[24],"as":[25,171,173],"seed":[26],"entropy.":[28],"Generally,":[29],"implementations":[30],"fully-digital":[32],"TRNGs":[33],"Field":[36],"Programmable":[37],"Gate":[38],"Array":[39],"(FPGA)":[40],"employ":[41],"several":[42],"ring":[43,73],"oscillators":[44,74],"implemented":[45,84],"large":[48],"number":[49,123],"Look-Up-Tables":[51],"(LUTs).":[52],"Differently,":[53],"in":[54],"this":[55,113],"work":[56],"we":[57],"propose":[58],"reliable":[60],"FPGA-based":[61],"architecture":[62,81],"TRNG":[65,133],"does":[67],"not":[68],"need":[69],"but":[75],"employs":[76],"only":[77,100],"on-board":[78],"primitives.":[79],"The":[80],"has":[82],"been":[83],"Xilinx":[87],"Ultrascale":[88],"XCKU040-2FFVA1156E":[89],"FPGA.":[90],"In":[91,112],"addition,":[92],"other":[93],"few":[94],"basic":[95],"logic":[96],"elements":[97],"are":[98],"employed":[99],"for":[101,108,183],"initial":[103],"overall":[104,137],"system":[105],"synchronization":[106],"and":[107,135,167],"post-processing":[110,148],"operation.":[111],"way,":[114],"it":[115],"is":[116],"possible":[117],"to":[118],"largely":[119],"reduce":[120],"needed":[122],"Configurable":[126],"Logic":[127],"Blocks":[128],"(CLBs)":[129],"so":[130,177],"limiting":[131],"complexity":[134],"its":[136],"power":[138],"consumption":[139],"without":[140],"affecting":[141],"resulting":[143],"throughput.":[144],"Finally,":[145],"after":[146],"procedure,":[149],"100Mbps":[151],"output":[152],"random":[153],"bitstream":[154],"provided":[155],"proposed":[158],"TRNG,":[159],"passed":[160],"all":[161],"National":[163],"Institute":[164],"Standards":[166],"Technology":[168],"(NIST)":[169],"tests":[170],"well":[172],"Kolmogorov-Smirnov":[175],"test":[176],"making":[178],"presented":[180],"solution":[181],"suitable":[182],"network":[184],"security":[185],"applications.":[186]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}