{"id":"https://openalex.org/W2801648437","doi":"https://doi.org/10.1109/iscas.2018.8351360","title":"A 5-Transistor Ternary Gain-Cell eDRAM with Parallel Sensing","display_name":"A 5-Transistor Ternary Gain-Cell eDRAM with Parallel Sensing","publication_year":2018,"publication_date":"2018-01-01","ids":{"openalex":"https://openalex.org/W2801648437","doi":"https://doi.org/10.1109/iscas.2018.8351360","mag":"2801648437"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2018.8351360","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2018.8351360","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5024705445","display_name":"Or Maltabashi","orcid":"https://orcid.org/0000-0002-6833-0829"},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]}],"countries":["IL"],"is_corresponding":true,"raw_author_name":"Or Maltabashi","raw_affiliation_strings":["Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel"],"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel","institution_ids":["https://openalex.org/I13955877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030530865","display_name":"Hanan Marinberg","orcid":null},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Hanan Marinberg","raw_affiliation_strings":["Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel"],"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel","institution_ids":["https://openalex.org/I13955877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034618529","display_name":"Robert Giterman","orcid":"https://orcid.org/0000-0002-1410-4746"},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Robert Giterman","raw_affiliation_strings":["Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel"],"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel","institution_ids":["https://openalex.org/I13955877"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026444183","display_name":"Adam Teman","orcid":"https://orcid.org/0000-0002-8233-4711"},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Adam Teman","raw_affiliation_strings":["Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel"],"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel","institution_ids":["https://openalex.org/I13955877"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5024705445"],"corresponding_institution_ids":["https://openalex.org/I13955877"],"apc_list":null,"apc_paid":null,"fwci":0.1288,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.45935311,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6963468194007874},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6012679934501648},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.5616381764411926},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5593563318252563},{"id":"https://openalex.org/keywords/ternary-operation","display_name":"Ternary operation","score":0.4945540130138397},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.46479126811027527},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.4488700032234192},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.382641464471817},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3781619071960449},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.32185831665992737},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2331969439983368},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.22612595558166504}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6963468194007874},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6012679934501648},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.5616381764411926},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5593563318252563},{"id":"https://openalex.org/C64452783","wikidata":"https://www.wikidata.org/wiki/Q1524945","display_name":"Ternary operation","level":2,"score":0.4945540130138397},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.46479126811027527},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.4488700032234192},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.382641464471817},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3781619071960449},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.32185831665992737},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2331969439983368},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.22612595558166504},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2018.8351360","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2018.8351360","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8700000047683716,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1619268095","https://openalex.org/W1871722508","https://openalex.org/W1970824390","https://openalex.org/W2082055514","https://openalex.org/W2093163564","https://openalex.org/W2108281294","https://openalex.org/W2114771440","https://openalex.org/W2118016286","https://openalex.org/W2151654658","https://openalex.org/W2167182882","https://openalex.org/W2343627454","https://openalex.org/W2398185263","https://openalex.org/W2511568025","https://openalex.org/W2733005606","https://openalex.org/W2754347129","https://openalex.org/W2765125965","https://openalex.org/W2769491465","https://openalex.org/W6744042956"],"related_works":["https://openalex.org/W3120961607","https://openalex.org/W2098207691","https://openalex.org/W3148568549","https://openalex.org/W1648516568","https://openalex.org/W361036515","https://openalex.org/W2269474412","https://openalex.org/W4386903460","https://openalex.org/W4211178602","https://openalex.org/W2537599394","https://openalex.org/W1518256384"],"abstract_inverted_index":{"Embedded":[0],"memories":[1],"dominate":[2],"area,":[3],"power,":[4],"and":[5,86,128],"cost":[6],"of":[7,72,88,134,155],"modern":[8],"VLSI":[9],"system-on-chips.":[10],"While":[11],"static":[12,149],"random":[13],"access":[14],"memory":[15],"(SRAM)":[16],"is":[17,70,96],"the":[18,84,89,165],"dominant":[19],"technology":[20,40,104],"for":[21,125,138],"implementing":[22],"these":[23],"memories,":[24],"Gain-cell":[25],"embedded":[26],"DRAM":[27],"(GC-eDRAM)":[28],"has":[29,41],"been":[30,42],"suggested":[31],"as":[32,55],"a":[33,51,65,78,99,107,129,152,160],"possible":[34],"alternative":[35],"in":[36,50,98,148,157,164],"recent":[37],"years.":[38],"This":[39],"shown":[43],"to":[44,57],"provide":[45],"low-power,":[46],"logic":[47],"compatible":[48],"storage":[49,90],"reduced":[52],"silicon":[53],"footprint,":[54],"compared":[56],"conventional":[58,161],"SRAM.":[59],"In":[60],"this":[61],"paper":[62],"we":[63],"suggest":[64],"novel":[66],"GC-eDRAM":[67],"topology":[68],"that":[69],"capable":[71],"storing":[73],"three":[74],"voltage":[75],"levels":[76],"within":[77],"single":[79],"cell,":[80],"further":[81],"improving":[82],"upon":[83],"area":[85],"energy-per-bit":[87],"solution.":[91],"The":[92,141],"proposed":[93,142],"ternary":[94,126,139],"gain-cell":[95],"designed":[97],"standard":[100],"CMOS":[101],"65":[102],"nm":[103],"node":[105],"using":[106],"low":[108],"overhead":[109],"<sup":[110],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[111,115,118,121],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">1</sup>":[112],"/":[113],"<sub":[114,120],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sub>":[116],"<i":[117],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">V</i>":[119],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">DD</sub>":[122],"write":[123],"driver":[124],"writes":[127],"parallel":[130],"sensing":[131],"scheme":[132],"composed":[133],"skewed":[135],"sense":[136],"inverters":[137],"readout.":[140],"approach":[143],"provides":[144],"over":[145],"3\u00d7":[146],"reduction":[147,154],"power":[150],"with":[151,159],"48%":[153],"area-per-bit":[156],"comparison":[158],"SRAM":[162],"cell":[163],"same":[166],"technology.":[167]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}