{"id":"https://openalex.org/W2801711510","doi":"https://doi.org/10.1109/iscas.2018.8351185","title":"A Novel Scan-In Scheme for CMOS/ReRAM Programmable Logic Circuits","display_name":"A Novel Scan-In Scheme for CMOS/ReRAM Programmable Logic Circuits","publication_year":2018,"publication_date":"2018-05-01","ids":{"openalex":"https://openalex.org/W2801711510","doi":"https://doi.org/10.1109/iscas.2018.8351185","mag":"2801711510"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2018.8351185","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2018.8351185","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071645986","display_name":"Md Musabbir Adnan","orcid":null},"institutions":[{"id":"https://openalex.org/I75027704","display_name":"University of Tennessee at Knoxville","ror":"https://ror.org/020f3ap87","country_code":"US","type":"education","lineage":["https://openalex.org/I75027704"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Md Musabbir Adnan","raw_affiliation_strings":["Department of Electrical Engineering & Computer Science, University of Tennesse Knoxville, Knoxville, Tennessee"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering & Computer Science, University of Tennesse Knoxville, Knoxville, Tennessee","institution_ids":["https://openalex.org/I75027704"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073702088","display_name":"Sherif Amer","orcid":null},"institutions":[{"id":"https://openalex.org/I75027704","display_name":"University of Tennessee at Knoxville","ror":"https://ror.org/020f3ap87","country_code":"US","type":"education","lineage":["https://openalex.org/I75027704"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sherif Amer","raw_affiliation_strings":["Department of Electrical Engineering & Computer Science, University of Tennesse Knoxville, Knoxville, Tennessee"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering & Computer Science, University of Tennesse Knoxville, Knoxville, Tennessee","institution_ids":["https://openalex.org/I75027704"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5047248181","display_name":"Garrett S. Rose","orcid":"https://orcid.org/0000-0003-3070-4087"},"institutions":[{"id":"https://openalex.org/I75027704","display_name":"University of Tennessee at Knoxville","ror":"https://ror.org/020f3ap87","country_code":"US","type":"education","lineage":["https://openalex.org/I75027704"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Garrett S. Rose","raw_affiliation_strings":["Department of Electrical Engineering & Computer Science, University of Tennesse Knoxville, Knoxville, Tennessee"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering & Computer Science, University of Tennesse Knoxville, Knoxville, Tennessee","institution_ids":["https://openalex.org/I75027704"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.1309,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.46783664,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/neuromorphic-engineering","display_name":"Neuromorphic engineering","score":0.8263883590698242},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.800351619720459},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7232865691184998},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6643568277359009},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5174413323402405},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.46870869398117065},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44121986627578735},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.41969674825668335},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.34640610218048096},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34063810110092163},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3200145363807678},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.2838444113731384},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2171197235584259},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1754174828529358},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.1076653003692627}],"concepts":[{"id":"https://openalex.org/C151927369","wikidata":"https://www.wikidata.org/wiki/Q1981312","display_name":"Neuromorphic engineering","level":3,"score":0.8263883590698242},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.800351619720459},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7232865691184998},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6643568277359009},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5174413323402405},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.46870869398117065},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44121986627578735},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.41969674825668335},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34640610218048096},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34063810110092163},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3200145363807678},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.2838444113731384},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2171197235584259},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1754174828529358},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.1076653003692627},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2018.8351185","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2018.8351185","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7699999809265137,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306084","display_name":"U.S. Department of Energy","ror":"https://ror.org/01bj3aw27"},{"id":"https://openalex.org/F4320315068","display_name":"University of Tennessee, Knoxville","ror":"https://ror.org/020f3ap87"},{"id":"https://openalex.org/F4320337547","display_name":"Laboratory Directed Research and Development","ror":"https://ror.org/01e41cf67"},{"id":"https://openalex.org/F4320338287","display_name":"Oak Ridge National Laboratory","ror":"https://ror.org/01qz5mb56"},{"id":"https://openalex.org/F4320338294","display_name":"Air Force Research Laboratory","ror":"https://ror.org/02e2egq70"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W162556487","https://openalex.org/W2101834447","https://openalex.org/W2129871911","https://openalex.org/W2162651880","https://openalex.org/W2168770118","https://openalex.org/W2400475751","https://openalex.org/W2555267483","https://openalex.org/W2594033018","https://openalex.org/W2756922823","https://openalex.org/W2759001553","https://openalex.org/W2760384882","https://openalex.org/W2802104007"],"related_works":["https://openalex.org/W4386475142","https://openalex.org/W2793181810","https://openalex.org/W2806638311","https://openalex.org/W2891417865","https://openalex.org/W2912892722","https://openalex.org/W1967489488","https://openalex.org/W2893723691","https://openalex.org/W2517651798","https://openalex.org/W2790329865","https://openalex.org/W2785635065"],"abstract_inverted_index":{"Resistive":[0],"RAM":[1],"(ReRAM)":[2],"devices":[3,36],"are":[4],"low":[5],"power,":[6],"fast":[7],"and":[8,23,33,70],"reliable":[9],"nanoelectronic":[10],"memory":[11,24,72,91],"devices,":[12],"which":[13],"have":[14],"proven":[15],"to":[16,61,66,82,88,103,107,111],"be":[17,40],"crucial":[18],"in":[19,31,42,55,59],"both":[20,68],"neuromorphic":[21,105],"hardware":[22],"design.":[25],"Despite":[26],"their":[27],"utility,":[28],"challenges":[29],"remain":[30],"forming":[32,50,123],"programming":[34,53,67],"these":[35],"before":[37],"they":[38],"can":[39],"used":[41],"a":[43,49,63,78,85,94,104,113],"system.":[44],"This":[45],"paper":[46],"builds":[47],"on":[48],"circuit,":[51],"incorporating":[52],"technique":[54],"the":[56,90,118],"same":[57],"circuit":[58],"addition":[60],"outlining":[62],"scan-in":[64,84],"approach":[65],"CMOS":[69],"ReRAM":[71],"elements.":[73],"The":[74,98],"proposed":[75],"scheme":[76],"utilizes":[77],"single":[79],"input":[80],"pin":[81],"serially":[83],"bit":[86],"sequence":[87],"program":[89],"elements,":[92],"leveraging":[93],"digital":[95],"control":[96],"circuitry.":[97],"suggested":[99],"protocol":[100],"is":[101,125],"applied":[102],"system":[106],"configure":[108],"synaptic":[109],"properties":[110],"implement":[112],"spiking":[114],"neural":[115],"network.":[116],"Lastly,":[117],"need":[119],"for":[120],"reduction":[121],"of":[122],"voltage":[124],"highlighted":[126],"with":[127],"power":[128],"dissipation":[129],"data":[130],"from":[131],"Spectre":[132],"simulation.":[133]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
