{"id":"https://openalex.org/W2800446783","doi":"https://doi.org/10.1109/iscas.2018.8351003","title":"Low-cost Technique for Measuring Clock Duty Cycle on FPGAs","display_name":"Low-cost Technique for Measuring Clock Duty Cycle on FPGAs","publication_year":2018,"publication_date":"2018-05-01","ids":{"openalex":"https://openalex.org/W2800446783","doi":"https://doi.org/10.1109/iscas.2018.8351003","mag":"2800446783"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2018.8351003","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2018.8351003","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5073497100","display_name":"Seongkwan Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I139264467","display_name":"Seoul National University","ror":"https://ror.org/04h9pn542","country_code":"KR","type":"education","lineage":["https://openalex.org/I139264467"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Seongkwan Lee","raw_affiliation_strings":["School of Electrical and Computer Engineering, Seoul National University, Seoul, Korea"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Seoul National University, Seoul, Korea","institution_ids":["https://openalex.org/I139264467"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100359404","display_name":"Taehwan Kim","orcid":"https://orcid.org/0000-0002-7681-9552"},"institutions":[{"id":"https://openalex.org/I139264467","display_name":"Seoul National University","ror":"https://ror.org/04h9pn542","country_code":"KR","type":"education","lineage":["https://openalex.org/I139264467"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Taehwan Kim","raw_affiliation_strings":["School of Electrical and Computer Engineering, Seoul National University, Seoul, Korea"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Seoul National University, Seoul, Korea","institution_ids":["https://openalex.org/I139264467"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5073497100"],"corresponding_institution_ids":["https://openalex.org/I139264467"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.03667011,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/duty-cycle","display_name":"Duty cycle","score":0.8774815797805786},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7191101312637329},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5259637832641602},{"id":"https://openalex.org/keywords/variable","display_name":"Variable (mathematics)","score":0.47835439443588257},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.4572032392024994},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44797343015670776},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4252853989601135},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.41435444355010986},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4125315546989441},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.40080660581588745},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.2884659469127655},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.28522902727127075},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2783472537994385},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.26728731393814087},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25968408584594727},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.177950918674469},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.13185575604438782},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09411337971687317}],"concepts":[{"id":"https://openalex.org/C199822604","wikidata":"https://www.wikidata.org/wiki/Q557120","display_name":"Duty cycle","level":3,"score":0.8774815797805786},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7191101312637329},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5259637832641602},{"id":"https://openalex.org/C182365436","wikidata":"https://www.wikidata.org/wiki/Q50701","display_name":"Variable (mathematics)","level":2,"score":0.47835439443588257},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.4572032392024994},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44797343015670776},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4252853989601135},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.41435444355010986},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4125315546989441},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.40080660581588745},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.2884659469127655},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.28522902727127075},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2783472537994385},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.26728731393814087},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25968408584594727},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.177950918674469},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.13185575604438782},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09411337971687317},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2018.8351003","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2018.8351003","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},{"id":"pmh:oai:s-space.snu.ac.kr:10371/186859","is_oa":false,"landing_page_url":"https://hdl.handle.net/10371/186859","pdf_url":null,"source":{"id":"https://openalex.org/S4306401345","display_name":"Seoul National University Open Repository (Seoul National University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I139264467","host_organization_name":"Seoul National University","host_organization_lineage":["https://openalex.org/I139264467"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.6499999761581421,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1984219569","https://openalex.org/W2200046639","https://openalex.org/W2417808006","https://openalex.org/W2572312547"],"related_works":["https://openalex.org/W2474747038","https://openalex.org/W4386968318","https://openalex.org/W3006003651","https://openalex.org/W2052455055","https://openalex.org/W2001020839","https://openalex.org/W2337711143","https://openalex.org/W4251123074","https://openalex.org/W2144282137","https://openalex.org/W2003180247","https://openalex.org/W2117814846"],"abstract_inverted_index":{"A":[0],"circuit":[1,14,38],"for":[2,8],"on-chip":[3],"measurement":[4,54],"of":[5,16,45,60,64,68],"duty":[6,62],"cycle":[7,63],"unknown":[9],"clock":[10,70],"is":[11,56,72],"demonstrated.":[12],"The":[13,48],"consists":[15],"variable":[17,31],"delay,":[18],"counter":[19],"and":[20,23,39],"AND":[21],"gate,":[22],"can":[24],"be":[25],"implemented":[26],"on":[27],"FPGA":[28],"that":[29,57],"has":[30],"delay":[32],"element":[33],"without":[34],"any":[35],"external":[36],"supporting":[37],"occupies":[40],"a":[41,65,75],"very":[42],"small":[43],"portion":[44],"the":[46,52,61],"FPGA.":[47],"major":[49],"benefit":[50],"over":[51],"previous":[53],"technology":[55],"statistical":[58],"analysis":[59],"large":[66],"number":[67],"continuous":[69],"cycles":[71],"possible":[73],"through":[74],"single":[76],"measurement.":[77]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}