{"id":"https://openalex.org/W2801144102","doi":"https://doi.org/10.1109/iscas.2018.8350974","title":"Gain Mismatch Insensitive Time-Interleaved DAC for CT Delta Sigma Modulator by application of a Three-State DAC","display_name":"Gain Mismatch Insensitive Time-Interleaved DAC for CT Delta Sigma Modulator by application of a Three-State DAC","publication_year":2018,"publication_date":"2018-01-01","ids":{"openalex":"https://openalex.org/W2801144102","doi":"https://doi.org/10.1109/iscas.2018.8350974","mag":"2801144102"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2018.8350974","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2018.8350974","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5034290581","display_name":"Ankesh Jain","orcid":"https://orcid.org/0000-0003-4109-6312"},"institutions":[{"id":"https://openalex.org/I196349391","display_name":"Universit\u00e4t Ulm","ror":"https://ror.org/032000t02","country_code":"DE","type":"education","lineage":["https://openalex.org/I196349391"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Ankesh Jain","raw_affiliation_strings":["Institute of Microelectronics, University of Ulm, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, University of Ulm, Germany","institution_ids":["https://openalex.org/I196349391"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5034938079","display_name":"Maurits Ortmanns","orcid":"https://orcid.org/0000-0002-3547-1596"},"institutions":[{"id":"https://openalex.org/I196349391","display_name":"Universit\u00e4t Ulm","ror":"https://ror.org/032000t02","country_code":"DE","type":"education","lineage":["https://openalex.org/I196349391"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Maurits Ortmanns","raw_affiliation_strings":["Institute of Microelectronics, University of Ulm, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, University of Ulm, Germany","institution_ids":["https://openalex.org/I196349391"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I196349391"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.05898175,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9925000071525574,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10320","display_name":"Neural Networks and Applications","score":0.972000002861023,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interleaving","display_name":"Interleaving","score":0.9467388987541199},{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.691405177116394},{"id":"https://openalex.org/keywords/converters","display_name":"Converters","score":0.6857186555862427},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.643415093421936},{"id":"https://openalex.org/keywords/delta-sigma-modulation","display_name":"Delta-sigma modulation","score":0.5505688786506653},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.501274585723877},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.43792325258255005},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.4293982982635498},{"id":"https://openalex.org/keywords/modulation","display_name":"Modulation (music)","score":0.4250907897949219},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.25089526176452637},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2175372838973999},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1593073010444641},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.11569258570671082},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.08153694868087769}],"concepts":[{"id":"https://openalex.org/C28034677","wikidata":"https://www.wikidata.org/wiki/Q17092530","display_name":"Interleaving","level":2,"score":0.9467388987541199},{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.691405177116394},{"id":"https://openalex.org/C2778422915","wikidata":"https://www.wikidata.org/wiki/Q10302051","display_name":"Converters","level":3,"score":0.6857186555862427},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.643415093421936},{"id":"https://openalex.org/C68754193","wikidata":"https://www.wikidata.org/wiki/Q1184820","display_name":"Delta-sigma modulation","level":3,"score":0.5505688786506653},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.501274585723877},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.43792325258255005},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.4293982982635498},{"id":"https://openalex.org/C123079801","wikidata":"https://www.wikidata.org/wiki/Q750240","display_name":"Modulation (music)","level":2,"score":0.4250907897949219},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.25089526176452637},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2175372838973999},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1593073010444641},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.11569258570671082},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.08153694868087769},{"id":"https://openalex.org/C24890656","wikidata":"https://www.wikidata.org/wiki/Q82811","display_name":"Acoustics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2018.8350974","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2018.8350974","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.5600000023841858}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W2017760583","https://openalex.org/W2030723369","https://openalex.org/W2050330628","https://openalex.org/W2107516488","https://openalex.org/W2121130638","https://openalex.org/W2151275222","https://openalex.org/W2155411941","https://openalex.org/W2402669108","https://openalex.org/W2525560078","https://openalex.org/W2752340009","https://openalex.org/W4285719527","https://openalex.org/W6743842906"],"related_works":["https://openalex.org/W3154683910","https://openalex.org/W1846734616","https://openalex.org/W1655266410","https://openalex.org/W2389051085","https://openalex.org/W2520281879","https://openalex.org/W2103861456","https://openalex.org/W3183433566","https://openalex.org/W1541346708","https://openalex.org/W4240663242","https://openalex.org/W1527371844"],"abstract_inverted_index":{"Time":[0],"interleaving":[1,22],"is":[2],"one":[3],"of":[4,13,32,63,81,100,113],"the":[5,10,20,25,30,44,48,64,79,96,101,111,114],"prominent":[6],"ways":[7],"to":[8,58],"increase":[9],"operating":[11],"speed":[12],"data":[14],"converters.":[15],"However,":[16],"mis-match":[17],"artifacts":[18],"among":[19],"time":[21,33,37,49,68],"sections":[23,70],"impair":[24],"performance":[26],"benefits":[27],"obtained":[28,94],"from":[29,95],"use":[31,80],"interleaving.":[34],"CTDSMs":[35],"with":[36],"interleaved":[38,50,69,73],"quantizers":[39],"are":[40],"particularly":[41],"affected":[42],"by":[43],"gain":[45,65],"mismatch":[46,66],"in":[47,71,106],"feedback":[51,88],"DAC.":[52],"We":[53],"present":[54],"a":[55,82,87],"circuit":[56],"technique":[57,77],"eliminate":[59],"this":[60],"adverse":[61],"effect":[62],"between":[67],"2\u00d7-time":[72],"quantizers.":[74],"The":[75,91],"proposed":[76,102],"involves":[78],"three":[83,103],"state":[84,104],"DAC":[85,89,105],"as":[86],"element.":[90],"simulations":[92],"results":[93],"schematic":[97],"level":[98],"implementation":[99],"40nm":[107],"CMOS":[108],"process":[109],"demonstrate":[110],"efficacy":[112],"presented":[115],"idea.":[116]},"counts_by_year":[{"year":2025,"cited_by_count":4},{"year":2022,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
