{"id":"https://openalex.org/W2802516784","doi":"https://doi.org/10.1109/iscas.2018.8350962","title":"Design of Majority Logic (ML) Based Approximate Full Adders","display_name":"Design of Majority Logic (ML) Based Approximate Full Adders","publication_year":2018,"publication_date":"2018-05-01","ids":{"openalex":"https://openalex.org/W2802516784","doi":"https://doi.org/10.1109/iscas.2018.8350962","mag":"2802516784"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2018.8350962","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2018.8350962","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100329646","display_name":"Tingting Zhang","orcid":"https://orcid.org/0000-0002-9483-8167"},"institutions":[{"id":"https://openalex.org/I9842412","display_name":"Nanjing University of Aeronautics and Astronautics","ror":"https://ror.org/01scyh794","country_code":"CN","type":"education","lineage":["https://openalex.org/I9842412"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Tingting Zhang","raw_affiliation_strings":["College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, China"],"affiliations":[{"raw_affiliation_string":"College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, China","institution_ids":["https://openalex.org/I9842412"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023734605","display_name":"Weiqiang Liu","orcid":"https://orcid.org/0000-0001-8398-8648"},"institutions":[{"id":"https://openalex.org/I9842412","display_name":"Nanjing University of Aeronautics and Astronautics","ror":"https://ror.org/01scyh794","country_code":"CN","type":"education","lineage":["https://openalex.org/I9842412"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Weiqiang Liu","raw_affiliation_strings":["College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, China"],"affiliations":[{"raw_affiliation_string":"College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, China","institution_ids":["https://openalex.org/I9842412"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088608996","display_name":"Emma McLarnon","orcid":null},"institutions":[{"id":"https://openalex.org/I126231945","display_name":"Queen's University Belfast","ror":"https://ror.org/00hswnk62","country_code":"GB","type":"education","lineage":["https://openalex.org/I126231945"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Emma McLarnon","raw_affiliation_strings":["ECIT, Queen's University Belfast, Belfast, UK"],"affiliations":[{"raw_affiliation_string":"ECIT, Queen's University Belfast, Belfast, UK","institution_ids":["https://openalex.org/I126231945"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079438004","display_name":"M\u00e1ire O\u05f3Neill","orcid":"https://orcid.org/0000-0002-6865-6212"},"institutions":[{"id":"https://openalex.org/I126231945","display_name":"Queen's University Belfast","ror":"https://ror.org/00hswnk62","country_code":"GB","type":"education","lineage":["https://openalex.org/I126231945"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Maire O'Neill","raw_affiliation_strings":["Queen's University Belfast, Belfast, Belfast, GB"],"affiliations":[{"raw_affiliation_string":"Queen's University Belfast, Belfast, Belfast, GB","institution_ids":["https://openalex.org/I126231945"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001979328","display_name":"Fabrizio Lombardi","orcid":"https://orcid.org/0000-0003-3152-3245"},"institutions":[{"id":"https://openalex.org/I12912129","display_name":"Northeastern University","ror":"https://ror.org/04t5xt781","country_code":"US","type":"education","lineage":["https://openalex.org/I12912129"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Fabrizio Lombardi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Northeastern University, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Northeastern University, USA","institution_ids":["https://openalex.org/I12912129"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5100329646"],"corresponding_institution_ids":["https://openalex.org/I9842412"],"apc_list":null,"apc_paid":null,"fwci":2.7781,"has_fulltext":false,"cited_by_count":44,"citation_normalized_percentile":{"value":0.91509187,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8844964504241943},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7154430150985718},{"id":"https://openalex.org/keywords/quantum-dot-cellular-automaton","display_name":"Quantum dot cellular automaton","score":0.5912672281265259},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.566577136516571},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5591675639152527},{"id":"https://openalex.org/keywords/cellular-automaton","display_name":"Cellular automaton","score":0.5323237776756287},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5267595648765564},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.4802244305610657},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.4613257944583893},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4608762562274933},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.43896088004112244},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.41972577571868896},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.38746172189712524},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3652857542037964},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.33155837655067444},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.33143433928489685},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.189327210187912},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10231432318687439},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09912613034248352},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08188030123710632}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8844964504241943},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7154430150985718},{"id":"https://openalex.org/C116523029","wikidata":"https://www.wikidata.org/wiki/Q7269040","display_name":"Quantum dot cellular automaton","level":3,"score":0.5912672281265259},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.566577136516571},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5591675639152527},{"id":"https://openalex.org/C35527583","wikidata":"https://www.wikidata.org/wiki/Q189156","display_name":"Cellular automaton","level":2,"score":0.5323237776756287},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5267595648765564},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.4802244305610657},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.4613257944583893},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4608762562274933},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.43896088004112244},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.41972577571868896},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.38746172189712524},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3652857542037964},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.33155837655067444},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.33143433928489685},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.189327210187912},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10231432318687439},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09912613034248352},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08188030123710632},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2018.8350962","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2018.8350962","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.qub.ac.uk/portal:publications/c225a232-398a-4c48-9871-ed2bd8da10fd","is_oa":false,"landing_page_url":"https://pure.qub.ac.uk/en/publications/c225a232-398a-4c48-9871-ed2bd8da10fd","pdf_url":null,"source":{"id":"https://openalex.org/S4306402319","display_name":"Research Portal (Queen's University Belfast)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I126231945","host_organization_name":"Queen's University Belfast","host_organization_lineage":["https://openalex.org/I126231945"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Zhang , T , Liu , W , McLarnon , E , O'Neill , M & Lombardi , F 2018 , Design of majority Logic (ML) based approximate full adders . in 2018 IEEE International Symposium on Circuits and Systems (ISCAS) - Proceedings . , 8350962 , Proceedings - IEEE International Symposium on Circuits and Systems , vol. 2018-May , Institute of Electrical and Electronics Engineers Inc. , 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 , Florence , Italy , 27/05/2018 . https://doi.org/10.1109/ISCAS.2018.8350962","raw_type":"contributionToPeriodical"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1979974858","https://openalex.org/W1998824039","https://openalex.org/W2005865544","https://openalex.org/W2017819499","https://openalex.org/W2020217519","https://openalex.org/W2027884601","https://openalex.org/W2104578404","https://openalex.org/W2128369966","https://openalex.org/W2143384051","https://openalex.org/W2155723362","https://openalex.org/W2160210493","https://openalex.org/W2535375934","https://openalex.org/W2757225496","https://openalex.org/W3141620748","https://openalex.org/W4206572362","https://openalex.org/W4237751615","https://openalex.org/W6744079932"],"related_works":["https://openalex.org/W2351310008","https://openalex.org/W2377041390","https://openalex.org/W2386022279","https://openalex.org/W659242671","https://openalex.org/W2243536805","https://openalex.org/W2181841040","https://openalex.org/W2913530739","https://openalex.org/W178466349","https://openalex.org/W2963391980","https://openalex.org/W2462231960"],"abstract_inverted_index":{"As":[0],"a":[1,22,64],"new":[2],"paradigm":[3],"in":[4,13,52,120],"the":[5,14,61,83,121,124],"nanoscale":[6],"technologies,":[7],"approximate":[8,66,75],"computing":[9],"enables":[10],"error":[11,113],"tolerance":[12],"computational":[15],"process;":[16],"it":[17],"has":[18,48],"also":[19,79,94],"emerged":[20],"as":[21,96,110,112],"low":[23],"power":[24],"design":[25,62],"methodology":[26],"for":[27],"arithmetic":[28],"circuits.":[29],"Majority":[30],"logic":[31],"(ML)":[32],"is":[33,93],"applicable":[34],"to":[35,88,129],"many":[36],"emerging":[37],"technologies":[38],"and":[39,81,108],"its":[40],"basic":[41],"building":[42],"block":[43],"(the":[44],"3-input":[45],"majority":[46,71],"voter)":[47],"been":[49],"extensively":[50],"used":[51],"digital":[53],"circuit":[54],"design.":[55],"In":[56],"this":[57],"paper,":[58],"we":[59],"propose":[60],"of":[63,85],"one-bit":[65],"full":[67,76],"adder":[68],"based":[69],"on":[70],"logic.":[72],"Furthermore,":[73],"multi-bit":[74],"adders":[77],"are":[78,101,127],"proposed":[80],"studied;":[82],"application":[84],"these":[86],"designs":[87,100,126],"quantum-dot":[89],"cellular":[90],"automata":[91],"(QCA)":[92],"presented":[95],"an":[97],"example.":[98],"The":[99],"evaluated":[102],"using":[103],"hardware":[104],"metrics":[105],"(including":[106],"delay":[107],"area)":[109],"well":[111],"metrics.":[114],"Compared":[115],"with":[116],"other":[117],"circuits":[118],"found":[119,128],"technical":[122],"literature,":[123],"optimal":[125],"offer":[130],"superior":[131],"performance.":[132]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":7},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":10},{"year":2022,"cited_by_count":11},{"year":2021,"cited_by_count":5},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":4}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}