{"id":"https://openalex.org/W2760174141","doi":"https://doi.org/10.1109/iscas.2017.8050969","title":"Memory fartitioning-based modulo scheduling for high-level synthesis","display_name":"Memory fartitioning-based modulo scheduling for high-level synthesis","publication_year":2017,"publication_date":"2017-05-01","ids":{"openalex":"https://openalex.org/W2760174141","doi":"https://doi.org/10.1109/iscas.2017.8050969","mag":"2760174141"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2017.8050969","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2017.8050969","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101715346","display_name":"Tianyi Lu","orcid":"https://orcid.org/0000-0001-6388-3419"},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Tianyi Lu","raw_affiliation_strings":["Tsinghua National Laboratory for Information Science and Technology Institute of Microelectronics, Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tsinghua National Laboratory for Information Science and Technology Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054524841","display_name":"Shouyi Yin","orcid":"https://orcid.org/0000-0003-2309-572X"},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shouyi Yin","raw_affiliation_strings":["Tsinghua National Laboratory for Information Science and Technology Institute of Microelectronics, Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tsinghua National Laboratory for Information Science and Technology Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110466012","display_name":"Xianqing Yao","orcid":null},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xianqing Yao","raw_affiliation_strings":["Tsinghua National Laboratory for Information Science and Technology Institute of Microelectronics, Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tsinghua National Laboratory for Information Science and Technology Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048421187","display_name":"Zhicong Xie","orcid":null},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhicong Xie","raw_affiliation_strings":["Tsinghua National Laboratory for Information Science and Technology Institute of Microelectronics, Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tsinghua National Laboratory for Information Science and Technology Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100358856","display_name":"Leibo Liu","orcid":"https://orcid.org/0000-0001-7548-4116"},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Leibo Liu","raw_affiliation_strings":["Tsinghua National Laboratory for Information Science and Technology Institute of Microelectronics, Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tsinghua National Laboratory for Information Science and Technology Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I99065089"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5036023084","display_name":"Shaojun Wei","orcid":"https://orcid.org/0000-0001-5117-7920"},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shaojun Wei","raw_affiliation_strings":["Tsinghua National Laboratory for Information Science and Technology Institute of Microelectronics, Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tsinghua National Laboratory for Information Science and Technology Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I99065089"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8345378637313843},{"id":"https://openalex.org/keywords/software-pipelining","display_name":"Software pipelining","score":0.7904960513114929},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6543317437171936},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5303282141685486},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5237148404121399},{"id":"https://openalex.org/keywords/modulo","display_name":"Modulo","score":0.48115837574005127},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.42499637603759766},{"id":"https://openalex.org/keywords/massively-parallel","display_name":"Massively parallel","score":0.4245007634162903},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.30188053846359253},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.26803767681121826},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.11303222179412842},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10342496633529663}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8345378637313843},{"id":"https://openalex.org/C188854837","wikidata":"https://www.wikidata.org/wiki/Q268469","display_name":"Software pipelining","level":3,"score":0.7904960513114929},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6543317437171936},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5303282141685486},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5237148404121399},{"id":"https://openalex.org/C54732982","wikidata":"https://www.wikidata.org/wiki/Q1415345","display_name":"Modulo","level":2,"score":0.48115837574005127},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.42499637603759766},{"id":"https://openalex.org/C190475519","wikidata":"https://www.wikidata.org/wiki/Q544384","display_name":"Massively parallel","level":2,"score":0.4245007634162903},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.30188053846359253},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.26803767681121826},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.11303222179412842},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10342496633529663},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2017.8050969","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2017.8050969","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6000000238418579,"id":"https://metadata.un.org/sdg/8","display_name":"Decent work and economic growth"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1996464317","https://openalex.org/W2039974221","https://openalex.org/W2071189607","https://openalex.org/W2071949763","https://openalex.org/W2093842169","https://openalex.org/W2123412205","https://openalex.org/W2143230897","https://openalex.org/W2147088458","https://openalex.org/W2153185479","https://openalex.org/W2168922271","https://openalex.org/W4239489018","https://openalex.org/W4246166885"],"related_works":["https://openalex.org/W2530146034","https://openalex.org/W1508051931","https://openalex.org/W4386554637","https://openalex.org/W4239489018","https://openalex.org/W2614194112","https://openalex.org/W2118578839","https://openalex.org/W3091672208","https://openalex.org/W2765564141","https://openalex.org/W1996464317","https://openalex.org/W2520229537"],"abstract_inverted_index":{"High-Level":[0],"Synthesis":[1],"(HLS)":[2],"has":[3],"been":[4],"widely":[5],"recognized":[6],"as":[7],"an":[8,45],"efficient":[9],"compilation":[10],"process":[11],"targeting":[12],"FPGAs":[13],"for":[14],"algorithm":[15],"evaluation":[16],"and":[17,27,59,71,79,101],"product":[18],"prototyping.":[19],"However,":[20],"the":[21,28,97,104,117],"massively":[22],"parallel":[23],"memory":[24,34,48,61,109],"access":[25],"demands":[26],"extremely":[29],"expensive":[30],"cost":[31],"of":[32,89,106],"single-bank":[33],"with":[35,75,116],"multi-port":[36],"have":[37],"impeded":[38],"loop":[39],"pipelining":[40,69,81,99],"performance.":[41,82],"Thus,":[42],"based":[43],"on":[44,113],"alternative":[46],"multi-bank":[47],"architecture,":[49],"a":[50,87],"joint":[51],"approach":[52,94],"that":[53,92],"employs":[54],"memory-aware":[55],"force":[56],"directed":[57],"scheduling":[58],"multi-cycle":[60],"partitioning":[62],"is":[63],"formally":[64],"proposed":[65],"to":[66],"achieve":[67,96],"legitimate":[68],"kernel":[70],"valid":[72],"bank":[73],"mapping":[74],"less":[76],"resource":[77],"consumption":[78],"optimal":[80,98],"The":[83],"experimental":[84],"results":[85],"over":[86],"variety":[88],"benchmarks":[90],"show":[91],"our":[93],"can":[95],"performance":[100],"meanwhile":[102],"reduce":[103],"number":[105],"multiple":[107],"independent":[108],"banks":[110],"by":[111],"55.1%":[112],"average,":[114],"compared":[115],"state-of-the-art":[118],"approaches.":[119]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2026-07-22T07:51:19.307946","created_date":"2025-10-10T00:00:00"}
