{"id":"https://openalex.org/W2759463585","doi":"https://doi.org/10.1109/iscas.2017.8050921","title":"Hybrid polymorphic logic gate using 6 terminal magnetic domain wall motion device","display_name":"Hybrid polymorphic logic gate using 6 terminal magnetic domain wall motion device","publication_year":2017,"publication_date":"2017-05-01","ids":{"openalex":"https://openalex.org/W2759463585","doi":"https://doi.org/10.1109/iscas.2017.8050921","mag":"2759463585"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2017.8050921","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2017.8050921","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://stars.library.ucf.edu/scopus2015/6637","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5091750431","display_name":"Farhana Parveen","orcid":"https://orcid.org/0000-0002-8348-7955"},"institutions":[{"id":"https://openalex.org/I106165777","display_name":"University of Central Florida","ror":"https://ror.org/036nfer12","country_code":"US","type":"education","lineage":["https://openalex.org/I106165777"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Farhana Parveen","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Central Florida, Orlando, FL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Central Florida, Orlando, FL, USA","institution_ids":["https://openalex.org/I106165777"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051680668","display_name":"Shaahin Angizi","orcid":"https://orcid.org/0000-0003-2289-6381"},"institutions":[{"id":"https://openalex.org/I106165777","display_name":"University of Central Florida","ror":"https://ror.org/036nfer12","country_code":"US","type":"education","lineage":["https://openalex.org/I106165777"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shaahin Angizi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Central Florida, Orlando, FL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Central Florida, Orlando, FL, USA","institution_ids":["https://openalex.org/I106165777"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036755436","display_name":"Zhezhi He","orcid":"https://orcid.org/0000-0002-6357-236X"},"institutions":[{"id":"https://openalex.org/I106165777","display_name":"University of Central Florida","ror":"https://ror.org/036nfer12","country_code":"US","type":"education","lineage":["https://openalex.org/I106165777"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhezhi He","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Central Florida, Orlando, FL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Central Florida, Orlando, FL, USA","institution_ids":["https://openalex.org/I106165777"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5047916979","display_name":"Deliang Fan","orcid":"https://orcid.org/0000-0002-7989-6297"},"institutions":[{"id":"https://openalex.org/I106165777","display_name":"University of Central Florida","ror":"https://ror.org/036nfer12","country_code":"US","type":"education","lineage":["https://openalex.org/I106165777"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Deliang Fan","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Central Florida, Orlando, FL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Central Florida, Orlando, FL, USA","institution_ids":["https://openalex.org/I106165777"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I106165777"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9955999851226807,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/xnor-gate","display_name":"XNOR gate","score":0.9113439917564392},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.7128391265869141},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.7111480832099915},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.6856601238250732},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.6821495890617371},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5973677635192871},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5696796178817749},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.5617229342460632},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5572922229766846},{"id":"https://openalex.org/keywords/nand-logic","display_name":"NAND logic","score":0.4839170575141907},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.4446074068546295},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4275895059108734},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.42659032344818115},{"id":"https://openalex.org/keywords/xor-gate","display_name":"XOR gate","score":0.4179063141345978},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3841639459133148},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.3098350167274475},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.28581541776657104},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22820454835891724},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.17540323734283447}],"concepts":[{"id":"https://openalex.org/C57684291","wikidata":"https://www.wikidata.org/wiki/Q1336142","display_name":"XNOR gate","level":4,"score":0.9113439917564392},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.7128391265869141},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.7111480832099915},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6856601238250732},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.6821495890617371},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5973677635192871},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5696796178817749},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.5617229342460632},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5572922229766846},{"id":"https://openalex.org/C7234692","wikidata":"https://www.wikidata.org/wiki/Q4116068","display_name":"NAND logic","level":4,"score":0.4839170575141907},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.4446074068546295},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4275895059108734},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.42659032344818115},{"id":"https://openalex.org/C28495749","wikidata":"https://www.wikidata.org/wiki/Q155516","display_name":"XOR gate","level":3,"score":0.4179063141345978},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3841639459133148},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.3098350167274475},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.28581541776657104},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22820454835891724},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.17540323734283447}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2017.8050921","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2017.8050921","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},{"id":"pmh:oai:stars.library.ucf.edu:scopus2015-7636","is_oa":true,"landing_page_url":"https://stars.library.ucf.edu/scopus2015/6637","pdf_url":null,"source":{"id":"https://openalex.org/S4210172555","display_name":"Journal of International Crisis and Risk Communication Research","issn_l":"2576-0017","issn":["2576-0017","2576-0025"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Scopus Export 2015-2019","raw_type":"text"}],"best_oa_location":{"id":"pmh:oai:stars.library.ucf.edu:scopus2015-7636","is_oa":true,"landing_page_url":"https://stars.library.ucf.edu/scopus2015/6637","pdf_url":null,"source":{"id":"https://openalex.org/S4210172555","display_name":"Journal of International Crisis and Risk Communication Research","issn_l":"2576-0017","issn":["2576-0017","2576-0025"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Scopus Export 2015-2019","raw_type":"text"},"sustainable_development_goals":[{"score":0.7599999904632568,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1524250393","https://openalex.org/W1524339075","https://openalex.org/W1692694227","https://openalex.org/W1992265433","https://openalex.org/W1994611297","https://openalex.org/W1997971931","https://openalex.org/W2020279094","https://openalex.org/W2024569531","https://openalex.org/W2065680810","https://openalex.org/W2077813824","https://openalex.org/W2096199318","https://openalex.org/W2120450604","https://openalex.org/W2130330964","https://openalex.org/W2149209089","https://openalex.org/W2152527810","https://openalex.org/W2153158393","https://openalex.org/W2169477751","https://openalex.org/W2342746717","https://openalex.org/W2441365091","https://openalex.org/W2912122427","https://openalex.org/W4244896417","https://openalex.org/W6682237725"],"related_works":["https://openalex.org/W4252993849","https://openalex.org/W3200424893","https://openalex.org/W2760452677","https://openalex.org/W4246304997","https://openalex.org/W2619968078","https://openalex.org/W1908137878","https://openalex.org/W1966410745","https://openalex.org/W2963778543","https://openalex.org/W2168217865","https://openalex.org/W2530808634"],"abstract_inverted_index":{"Polymorphic":[0],"gates":[1],"are":[2,45],"capable":[3],"of":[4,62],"adapting":[5],"to":[6,48,57,120,144],"multiple":[7],"functionalities":[8],"depending":[9],"on":[10,27],"the":[11,46,74],"application":[12],"and":[13,117,127,142,156],"need.":[14],"In":[15],"this":[16],"paper,":[17],"we":[18,42,44],"propose":[19],"a":[20,28,50,59,83,108,149],"hybrid":[21],"spin-CMOS":[22],"polymorphic":[23,52,90,118],"logic":[24,65,91,115,145],"gate":[25,53,92],"based":[26],"novel":[29],"6":[30],"terminal":[31],"composite":[32],"magnetic":[33],"domain":[34],"wall":[35],"motion":[36],"device":[37],"structure.":[38],"As":[39],"far":[40],"as":[41],"know,":[43],"first":[47],"present":[49],"single":[51],"that":[54,82],"is":[55],"able":[56],"perform":[58],"full":[60,84,101],"set":[61],"2-input":[63],"Boolean":[64],"functions":[66],"(i.e.":[67],"AND/NAND,":[68],"OR/NOR,":[69],"NOT,":[70],"XOR/XNOR)":[71],"by":[72,113],"configuring":[73],"applied":[75],"keys.":[76],"The":[77],"SPICE":[78],"device-circuit":[79],"co-simulation":[80],"indicates":[81],"adder":[85,102],"design":[86,134],"using":[87],"our":[88,132],"proposed":[89,133],"shows":[93],"45.74%":[94],"power":[95,139,154],"reduction":[96],"compared":[97],"with":[98],"traditional":[99],"CMOS":[100],"design.":[103],"Moreover,":[104],"it":[105],"can":[106],"be":[107],"promising":[109],"hardware":[110],"security":[111],"primitive":[112],"implementing":[114],"locking":[116],"transformation":[119],"protect":[121],"Integrated":[122],"Circuit":[123],"(IC)":[124],"against":[125],"counterfeiting":[126],"reverse":[128],"engineering.":[129],"To":[130],"summarize,":[131],"simultaneously":[135],"provides":[136],"non-volatility,":[137],"low":[138],"consumption,":[140],"compactness":[141],"polymorphism":[143],"circuits,":[146],"which":[147],"opens":[148],"new":[150],"paradigm":[151],"for":[152],"future":[153],"efficient":[155],"secured":[157],"computing.":[158]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}