{"id":"https://openalex.org/W2757996710","doi":"https://doi.org/10.1109/iscas.2017.8050519","title":"An academic EDA suite for the full-custom design of mixed-mode integrated circuits","display_name":"An academic EDA suite for the full-custom design of mixed-mode integrated circuits","publication_year":2017,"publication_date":"2017-05-01","ids":{"openalex":"https://openalex.org/W2757996710","doi":"https://doi.org/10.1109/iscas.2017.8050519","mag":"2757996710"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2017.8050519","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2017.8050519","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5015112893","display_name":"Jofre Pallar\u00e8s","orcid":"https://orcid.org/0000-0002-2265-3999"},"institutions":[{"id":"https://openalex.org/I4210160312","display_name":"Institut de Microelectr\u00f2nica de Barcelona","ror":"https://ror.org/04pnym676","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210147934","https://openalex.org/I4210160312"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"J. Pallares","raw_affiliation_strings":["Institut de Microelectr\u00f2nica de Barcelona, IMB-CNM(CSIC)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institut de Microelectr\u00f2nica de Barcelona, IMB-CNM(CSIC)","institution_ids":["https://openalex.org/I4210160312"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072361677","display_name":"K. Sabine","orcid":null},"institutions":[{"id":"https://openalex.org/I4210115819","display_name":"Gidropribor","ror":"https://ror.org/01ftfrf48","country_code":"RU","type":"facility","lineage":["https://openalex.org/I4210115819"]}],"countries":["RU"],"is_corresponding":false,"raw_author_name":"K. Sabine","raw_affiliation_strings":["Peardrop Design Systems Ltd"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Peardrop Design Systems Ltd","institution_ids":["https://openalex.org/I4210115819"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007355640","display_name":"Llu\u00eds Ter\u00e9s","orcid":"https://orcid.org/0000-0002-9263-411X"},"institutions":[{"id":"https://openalex.org/I123044942","display_name":"Universitat Aut\u00f2noma de Barcelona","ror":"https://ror.org/052g8jq94","country_code":"ES","type":"education","lineage":["https://openalex.org/I123044942"]},{"id":"https://openalex.org/I4210160312","display_name":"Institut de Microelectr\u00f2nica de Barcelona","ror":"https://ror.org/04pnym676","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210147934","https://openalex.org/I4210160312"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"L. Teres","raw_affiliation_strings":["Dept. of Microelectronics and Electronic Systems, Universitat Autonoma de Barcelona","IMB-CNM(CSIC), Institut de Microelectronica de Barcelona"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Microelectronics and Electronic Systems, Universitat Autonoma de Barcelona","institution_ids":["https://openalex.org/I123044942"]},{"raw_affiliation_string":"IMB-CNM(CSIC), Institut de Microelectronica de Barcelona","institution_ids":["https://openalex.org/I4210160312"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5056485115","display_name":"Francisco Serra-Graells","orcid":"https://orcid.org/0000-0002-7274-1911"},"institutions":[{"id":"https://openalex.org/I123044942","display_name":"Universitat Aut\u00f2noma de Barcelona","ror":"https://ror.org/052g8jq94","country_code":"ES","type":"education","lineage":["https://openalex.org/I123044942"]},{"id":"https://openalex.org/I4210160312","display_name":"Institut de Microelectr\u00f2nica de Barcelona","ror":"https://ror.org/04pnym676","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210147934","https://openalex.org/I4210160312"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"F. Serra-Graells","raw_affiliation_strings":["Dept. of Microelectronics and Electronic Systems, Universitat Autonoma de Barcelona","IMB-CNM(CSIC), Institut de Microelectronica de Barcelona"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Microelectronics and Electronic Systems, Universitat Autonoma de Barcelona","institution_ids":["https://openalex.org/I123044942"]},{"raw_affiliation_string":"IMB-CNM(CSIC), Institut de Microelectronica de Barcelona","institution_ids":["https://openalex.org/I4210160312"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.514,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.8032739,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.7788307666778564},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6501803398132324},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6016141176223755},{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.5991466641426086},{"id":"https://openalex.org/keywords/parasitic-extraction","display_name":"Parasitic extraction","score":0.5860192775726318},{"id":"https://openalex.org/keywords/suite","display_name":"Suite","score":0.5660016536712646},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.564087450504303},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.5574013590812683},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.5437111258506775},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5287527441978455},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.5160865187644958},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4950810968875885},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4927575886249542},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4862319529056549},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.4463474154472351},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.43184739351272583},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.42500829696655273},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.41971880197525024},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3821646571159363},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.3588141202926636},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2499915361404419},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.13260918855667114},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.12744534015655518},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11602634191513062}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.7788307666778564},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6501803398132324},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6016141176223755},{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.5991466641426086},{"id":"https://openalex.org/C159818811","wikidata":"https://www.wikidata.org/wiki/Q7135947","display_name":"Parasitic extraction","level":2,"score":0.5860192775726318},{"id":"https://openalex.org/C79581498","wikidata":"https://www.wikidata.org/wiki/Q1367530","display_name":"Suite","level":2,"score":0.5660016536712646},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.564087450504303},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.5574013590812683},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.5437111258506775},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5287527441978455},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.5160865187644958},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4950810968875885},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4927575886249542},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4862319529056549},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.4463474154472351},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.43184739351272583},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.42500829696655273},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.41971880197525024},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3821646571159363},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.3588141202926636},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2499915361404419},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13260918855667114},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.12744534015655518},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11602634191513062},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C166957645","wikidata":"https://www.wikidata.org/wiki/Q23498","display_name":"Archaeology","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C95457728","wikidata":"https://www.wikidata.org/wiki/Q309","display_name":"History","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2017.8050519","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2017.8050519","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W95401678","https://openalex.org/W1536945048","https://openalex.org/W1566907904","https://openalex.org/W1580014081","https://openalex.org/W2084510002","https://openalex.org/W2493943245"],"related_works":["https://openalex.org/W4292182797","https://openalex.org/W2583707817","https://openalex.org/W2148021977","https://openalex.org/W2304374807","https://openalex.org/W2142651762","https://openalex.org/W85694287","https://openalex.org/W2253173388","https://openalex.org/W2904595763","https://openalex.org/W2143930978","https://openalex.org/W4239381562"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"a":[3,72,78],"free":[4],"and":[5,24,42,48,65,105,117],"complete":[6],"EDA":[7,22,100],"framework":[8,101],"for":[9,75,113],"teaching":[10],"CMOS":[11,80],"full-custom":[12],"design":[13,27],"of":[14,21,88,97],"mixed-signal":[15],"integrated":[16],"circuits.":[17],"The":[18],"presented":[19,99],"set":[20],"tools":[23,110],"associated":[25],"physical":[26],"kit":[28],"should":[29],"allow":[30],"students":[31],"to":[32,84],"gain":[33],"hands-on":[34],"experience":[35],"on":[36,71],"schematic":[37],"entry,":[38],"both":[39,102,114],"at":[40,103,106],"system":[41,46],"circuit":[43,52],"levels,":[44],"HDL":[45],"simulation":[47,64],"block":[49],"specification,":[50],"automatic":[51],"optimization,":[53],"PCell-based":[54],"netlist-driven":[55],"layout,":[56],"interactive":[57],"DRC,":[58],"LVS,":[59],"3D":[60],"parasitics":[61],"extraction,":[62],"post-layout":[63],"tape-out.":[66],"A":[67],"case":[68],"study":[69],"based":[70],"\u0394\u03a3":[73],"modulator":[74],"ADC":[76],"in":[77],"simple":[79],"technology":[81],"is":[82],"supplied":[83],"illustrate":[85],"the":[86,89,98],"capabilities":[87],"proposed":[90],"environment.":[91],"Students":[92],"can":[93],"easily":[94],"make":[95],"use":[96],"laboratory":[104],"home,":[107],"since":[108],"all":[109],"are":[111],"available":[112],"MS":[115],"Windows":[116],"Linux":[118],"platforms.":[119]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":3}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
