{"id":"https://openalex.org/W2760059708","doi":"https://doi.org/10.1109/iscas.2017.8050351","title":"A 5-bit phase-interpolator-based fractional-N frequency divider for digital phase-locked loops","display_name":"A 5-bit phase-interpolator-based fractional-N frequency divider for digital phase-locked loops","publication_year":2017,"publication_date":"2017-05-01","ids":{"openalex":"https://openalex.org/W2760059708","doi":"https://doi.org/10.1109/iscas.2017.8050351","mag":"2760059708"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2017.8050351","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2017.8050351","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5028628375","display_name":"Jianfu Lin","orcid":"https://orcid.org/0000-0001-8195-9317"},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Jianfu Lin","raw_affiliation_strings":["Institute of Microelectronics, Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089","https://openalex.org/I4210119392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063888012","display_name":"Hanjun Jiang","orcid":"https://orcid.org/0000-0003-4911-0748"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hanjun Jiang","raw_affiliation_strings":["Institute of Microelectronics, Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089","https://openalex.org/I4210119392"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052727227","display_name":"Baoyong Chi","orcid":"https://orcid.org/0000-0003-4399-4423"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Baoyong Chi","raw_affiliation_strings":["Tsinghua National Laboratory for Information Science and Technology, Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Tsinghua National Laboratory for Information Science and Technology, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5028628375"],"corresponding_institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I99065089"],"apc_list":null,"apc_paid":null,"fwci":0.43,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.65666045,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.9923999905586243,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/frequency-divider","display_name":"Frequency divider","score":0.8128893375396729},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5722482204437256},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.5632381439208984},{"id":"https://openalex.org/keywords/resistor","display_name":"Resistor","score":0.5517256259918213},{"id":"https://openalex.org/keywords/dbc","display_name":"dBc","score":0.5210675597190857},{"id":"https://openalex.org/keywords/frequency-multiplier","display_name":"Frequency multiplier","score":0.48409807682037354},{"id":"https://openalex.org/keywords/delta-sigma-modulation","display_name":"Delta-sigma modulation","score":0.47439053654670715},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.47278285026550293},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.46945732831954956},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.43826109170913696},{"id":"https://openalex.org/keywords/frequency-synthesizer","display_name":"Frequency synthesizer","score":0.4246799349784851},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4191684126853943},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.40670204162597656},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3509117364883423},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2866031229496002},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.26845401525497437}],"concepts":[{"id":"https://openalex.org/C74982907","wikidata":"https://www.wikidata.org/wiki/Q1455624","display_name":"Frequency divider","level":3,"score":0.8128893375396729},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5722482204437256},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.5632381439208984},{"id":"https://openalex.org/C137488568","wikidata":"https://www.wikidata.org/wiki/Q5321","display_name":"Resistor","level":3,"score":0.5517256259918213},{"id":"https://openalex.org/C193523891","wikidata":"https://www.wikidata.org/wiki/Q1771950","display_name":"dBc","level":3,"score":0.5210675597190857},{"id":"https://openalex.org/C146002875","wikidata":"https://www.wikidata.org/wiki/Q1074289","display_name":"Frequency multiplier","level":3,"score":0.48409807682037354},{"id":"https://openalex.org/C68754193","wikidata":"https://www.wikidata.org/wiki/Q1184820","display_name":"Delta-sigma modulation","level":3,"score":0.47439053654670715},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.47278285026550293},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.46945732831954956},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.43826109170913696},{"id":"https://openalex.org/C182099602","wikidata":"https://www.wikidata.org/wiki/Q2660678","display_name":"Frequency synthesizer","level":4,"score":0.4246799349784851},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4191684126853943},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.40670204162597656},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3509117364883423},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2866031229496002},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.26845401525497437},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2017.8050351","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2017.8050351","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5400000214576721,"display_name":"Peace, Justice and strong institutions","id":"https://metadata.un.org/sdg/16"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W2018588972","https://openalex.org/W2022512492","https://openalex.org/W2023401960","https://openalex.org/W2072937223","https://openalex.org/W2084894221","https://openalex.org/W2112489816","https://openalex.org/W2120500930","https://openalex.org/W3142120744"],"related_works":["https://openalex.org/W2148435004","https://openalex.org/W3095898867","https://openalex.org/W1975478216","https://openalex.org/W2099990255","https://openalex.org/W3207257560","https://openalex.org/W2167684701","https://openalex.org/W2185082472","https://openalex.org/W1915959989","https://openalex.org/W2358217230","https://openalex.org/W2513253674"],"abstract_inverted_index":{"A":[0,16],"fractional-N":[1,82,136],"frequency":[2,83,137],"divider":[3,84,138],"based":[4,119],"on":[5,120],"a":[6,95,115],"5-bit":[7],"phase":[8,53,68,77],"interpolator":[9],"(PI)":[10],"is":[11,26,56,85,122,139],"presented":[12],"in":[13,87],"this":[14],"paper.":[15],"novel":[17],"PI":[18,113],"unit":[19],"cell":[20],"with":[21,98],"the":[22,30,34,37,49,64,67,71,75,99,109,112,130,135],"switched":[23],"resistor":[24],"loads":[25],"proposed":[27,57,81],"to":[28,58],"break":[29],"constraint":[31],"brought":[32],"by":[33,134],"variation":[35],"of":[36,46,66,74,111],"common-mode":[38],"output":[39],"voltage,":[40],"providing":[41],"an":[42,60],"extra":[43],"design":[44],"degree":[45],"freedom":[47],"for":[48],"optimization.":[50],"An":[51],"all-digital":[52],"rotating":[54],"scheme":[55],"achieve":[59],"excellent":[61],"balance":[62],"between":[63],"robustness":[65],"interpolation":[69],"and":[70],"speed":[72],"limitation":[73],"synthesized":[76],"control":[78],"circuit.":[79],"The":[80,124],"designed":[86],"65-nm":[88],"CMOS":[89],"technology,":[90],"dissipating":[91],"1.13-1.3":[92],"mW":[93],"from":[94],"1.2-V":[96],"supply":[97],"quadrature":[100],"input":[101],"signals":[102],"at":[103],"2.4":[104],"GHz.":[105],"To":[106],"further":[107],"evaluate":[108],"influence":[110],"non-linearity,":[114],"behavioral":[116,125],"simulation":[117,126],"model":[118],"Simulink":[121],"built.":[123],"results":[127],"show":[128],"that":[129],"in-band":[131],"spur":[132],"induced":[133],"-51.8":[140],"dBc.":[141]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}