{"id":"https://openalex.org/W2756825072","doi":"https://doi.org/10.1109/iscas.2017.8050284","title":"A wide tuning-range ADFLL for mW-SoCs with dithering-enhanced accuracy in 65 nm CMOS","display_name":"A wide tuning-range ADFLL for mW-SoCs with dithering-enhanced accuracy in 65 nm CMOS","publication_year":2017,"publication_date":"2017-05-01","ids":{"openalex":"https://openalex.org/W2756825072","doi":"https://doi.org/10.1109/iscas.2017.8050284","mag":"2756825072"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2017.8050284","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2017.8050284","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038237473","display_name":"David E. Bellasi","orcid":"https://orcid.org/0000-0001-9295-1919"},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":true,"raw_author_name":"David Bellasi","raw_affiliation_strings":["Dept. of Information Technology and Electrical Engineering (D-ITET), ETH Z\u00fcrich, Z\u00fcrich, Switzerland"],"affiliations":[{"raw_affiliation_string":"Dept. of Information Technology and Electrical Engineering (D-ITET), ETH Z\u00fcrich, Z\u00fcrich, Switzerland","institution_ids":["https://openalex.org/I35440088"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032599331","display_name":"Philipp Sch\u00f6nle","orcid":"https://orcid.org/0000-0002-1586-6988"},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Philipp Schonle","raw_affiliation_strings":["Dept. of Information Technology and Electrical Engineering (D-ITET), ETH Z\u00fcrich, Z\u00fcrich, Switzerland"],"affiliations":[{"raw_affiliation_string":"Dept. of Information Technology and Electrical Engineering (D-ITET), ETH Z\u00fcrich, Z\u00fcrich, Switzerland","institution_ids":["https://openalex.org/I35440088"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111442846","display_name":"Qiuting Huang","orcid":null},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Qiuting Huang","raw_affiliation_strings":["Dept. of Information Technology and Electrical Engineering (D-ITET), ETH Z\u00fcrich, Z\u00fcrich, Switzerland"],"affiliations":[{"raw_affiliation_string":"Dept. of Information Technology and Electrical Engineering (D-ITET), ETH Z\u00fcrich, Z\u00fcrich, Switzerland","institution_ids":["https://openalex.org/I35440088"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043408422","display_name":"Luca Benini","orcid":"https://orcid.org/0000-0001-8068-3806"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]},{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH","IT"],"is_corresponding":false,"raw_author_name":"Luca Benini","raw_affiliation_strings":["Dept. of Electrical, Electronic, and Information Engineering (DEI), University of Bologna, Bologna, Italy","Dept. of Information Technology and Electrical Engineering (D-ITET), ETH Z\u00fcrich, Z\u00fcrich, Switzerland"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical, Electronic, and Information Engineering (DEI), University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]},{"raw_affiliation_string":"Dept. of Information Technology and Electrical Engineering (D-ITET), ETH Z\u00fcrich, Z\u00fcrich, Switzerland","institution_ids":["https://openalex.org/I35440088"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5038237473"],"corresponding_institution_ids":["https://openalex.org/I35440088"],"apc_list":null,"apc_paid":null,"fwci":0.5734,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.69884597,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.8253812789916992},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7068979144096375},{"id":"https://openalex.org/keywords/dither","display_name":"Dither","score":0.6508010625839233},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.5731896758079529},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.5079792141914368},{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.4610878825187683},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.45087477564811707},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.42034652829170227},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.4186820685863495},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.41521376371383667},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.38426727056503296},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.2583334743976593},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22018340229988098},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09181344509124756}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.8253812789916992},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7068979144096375},{"id":"https://openalex.org/C70451592","wikidata":"https://www.wikidata.org/wiki/Q376493","display_name":"Dither","level":3,"score":0.6508010625839233},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.5731896758079529},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.5079792141914368},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.4610878825187683},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.45087477564811707},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.42034652829170227},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.4186820685863495},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.41521376371383667},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.38426727056503296},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.2583334743976593},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22018340229988098},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09181344509124756},{"id":"https://openalex.org/C9083635","wikidata":"https://www.wikidata.org/wiki/Q2133535","display_name":"Noise shaping","level":2,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2017.8050284","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2017.8050284","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},{"id":"pmh:oai:cris.unibo.it:11585/624734","is_oa":false,"landing_page_url":"http://hdl.handle.net/11585/624734","pdf_url":null,"source":{"id":"https://openalex.org/S4306402579","display_name":"Archivio istituzionale della ricerca (Alma Mater Studiorum Universit\u00e0 di Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210117483","host_organization_name":"Istituto di Ematologia di Bologna","host_organization_lineage":["https://openalex.org/I4210117483"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8199999928474426,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1511246636","https://openalex.org/W1998264560","https://openalex.org/W2041947839","https://openalex.org/W2086249599","https://openalex.org/W2118154600","https://openalex.org/W2118565267","https://openalex.org/W2142324750","https://openalex.org/W2147419116"],"related_works":["https://openalex.org/W2301158783","https://openalex.org/W2133120878","https://openalex.org/W2085381517","https://openalex.org/W2376956425","https://openalex.org/W2132410050","https://openalex.org/W1972664199","https://openalex.org/W2071924372","https://openalex.org/W4284685595","https://openalex.org/W2377552037","https://openalex.org/W4200596515"],"abstract_inverted_index":{"We":[0],"present":[1],"an":[2],"integer-N":[3],"all-digital":[4],"frequency-locked":[5],"loop":[6],"(ADFLL)":[7],"suitable":[8],"for":[9],"dynamic":[10],"voltage":[11],"and":[12,29,52,77,101,145,159],"frequency":[13],"scaling":[14],"in":[15,39,72,132],"system-on-chips":[16],"targeting":[17],"mW-consumption.":[18],"The":[19,85,109],"proposed":[20],"ADFLL":[21],"operates":[22],"with":[23,153,163],"a":[24,31,40,61,81,104,119,125],"32":[25],"kHz":[26,45],"clock":[27,33,75,87,122],"reference,":[28],"offers":[30],"large":[32],"multiplication":[34],"factor":[35,89],"of":[36,68,92,114,143],"32786,":[37],"resulting":[38],"wide":[41],"tuning-range":[42],"from":[43,124],"19":[44],"to":[46,53],"1.048":[47],"GHz":[48],"at":[49,56,103,118,146,156,166],"1.2":[50,157,164],"V":[51],"250":[54],"MHz":[55,106,127,148],"0.8":[57,167],"V,.":[58],"It":[59],"incorporates":[60],"jitter":[62,97,113],"reduction":[63,91],"technique":[64],"enabling":[65],"the":[66,93],"generation":[67],"accurate":[69],"low-rate":[70],"clocks":[71],"ADFLLs,":[73],"combining":[74],"division":[76,88],"dithering":[78],"based":[79],"on":[80],"1st-order":[82],"digital":[83],"\u03a3\u0394-modulator.":[84],"measured":[86,117],"dependent":[90],"peak":[94,111],"cycle-to-cycle":[95],"(C2C)":[96],"was":[98,116],"between":[99],"40%":[100],"70%":[102],"200":[105],"DCO":[107,128],"clock.":[108,129],"lowest":[110],"C2C":[112],"0.14%":[115],"3.15MHz":[120],"output":[121],"derived":[123],"800":[126],"A":[130],"prototype":[131],"UMC":[133],"65":[134],"nm":[135],"CMOS":[136],"occupies":[137],"0.013":[138],"mm":[139],"<sup":[140],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[141],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[142],"area,":[144],"100":[147],"consumes":[149],"605":[150],"\u03bcW":[151,161],"(scaling":[152,162],"3":[154],"\u03bcW/MHz)":[155,165],"V,":[158],"205":[160],"V.":[168]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}