{"id":"https://openalex.org/W2517056423","doi":"https://doi.org/10.1109/iscas.2016.7538954","title":"Power-aware through-silicon-via minimization by partitioning finite state machine with datapath","display_name":"Power-aware through-silicon-via minimization by partitioning finite state machine with datapath","publication_year":2016,"publication_date":"2016-05-01","ids":{"openalex":"https://openalex.org/W2517056423","doi":"https://doi.org/10.1109/iscas.2016.7538954","mag":"2517056423"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2016.7538954","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2016.7538954","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083598563","display_name":"Ayub Chin Abdullah","orcid":null},"institutions":[{"id":"https://openalex.org/I4576418","display_name":"University of Technology Malaysia","ror":"https://ror.org/026w31v75","country_code":"MY","type":"education","lineage":["https://openalex.org/I4576418"]}],"countries":["MY"],"is_corresponding":true,"raw_author_name":"Ayub Chin Abdullah","raw_affiliation_strings":["Embedded System Research Laboratory, Universiti Teknologi Malaysia, Kuala Lumpur, Malaysia"],"affiliations":[{"raw_affiliation_string":"Embedded System Research Laboratory, Universiti Teknologi Malaysia, Kuala Lumpur, Malaysia","institution_ids":["https://openalex.org/I4576418"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018366020","display_name":"Chia Yee Ooi","orcid":"https://orcid.org/0000-0003-2307-4048"},"institutions":[{"id":"https://openalex.org/I4576418","display_name":"University of Technology Malaysia","ror":"https://ror.org/026w31v75","country_code":"MY","type":"education","lineage":["https://openalex.org/I4576418"]}],"countries":["MY"],"is_corresponding":false,"raw_author_name":"Chia Yee Ooi","raw_affiliation_strings":["Embedded System Research Laboratory, Universiti Teknologi Malaysia, Kuala Lumpur, Malaysia"],"affiliations":[{"raw_affiliation_string":"Embedded System Research Laboratory, Universiti Teknologi Malaysia, Kuala Lumpur, Malaysia","institution_ids":["https://openalex.org/I4576418"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103710735","display_name":"Nordinah Bt Ismail","orcid":null},"institutions":[{"id":"https://openalex.org/I4576418","display_name":"University of Technology Malaysia","ror":"https://ror.org/026w31v75","country_code":"MY","type":"education","lineage":["https://openalex.org/I4576418"]}],"countries":["MY"],"is_corresponding":false,"raw_author_name":"Nordinah Bt Ismail","raw_affiliation_strings":["Embedded System Research Laboratory, Universiti Teknologi Malaysia, Kuala Lumpur, Malaysia"],"affiliations":[{"raw_affiliation_string":"Embedded System Research Laboratory, Universiti Teknologi Malaysia, Kuala Lumpur, Malaysia","institution_ids":["https://openalex.org/I4576418"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5048716164","display_name":"Nurita Binti Mohammad","orcid":null},"institutions":[{"id":"https://openalex.org/I4576418","display_name":"University of Technology Malaysia","ror":"https://ror.org/026w31v75","country_code":"MY","type":"education","lineage":["https://openalex.org/I4576418"]}],"countries":["MY"],"is_corresponding":false,"raw_author_name":"Nurita Binti Mohammad","raw_affiliation_strings":["Embedded System Research Laboratory, Universiti Teknologi Malaysia, Kuala Lumpur, Malaysia"],"affiliations":[{"raw_affiliation_string":"Embedded System Research Laboratory, Universiti Teknologi Malaysia, Kuala Lumpur, Malaysia","institution_ids":["https://openalex.org/I4576418"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5083598563"],"corresponding_institution_ids":["https://openalex.org/I4576418"],"apc_list":null,"apc_paid":null,"fwci":0.3153,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.57682904,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1942","last_page":"1945"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.958939254283905},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.6303945183753967},{"id":"https://openalex.org/keywords/integer-programming","display_name":"Integer programming","score":0.6170469522476196},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6166098713874817},{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.5957371592521667},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5020647048950195},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4855892062187195},{"id":"https://openalex.org/keywords/discrete-cosine-transform","display_name":"Discrete cosine transform","score":0.4827924966812134},{"id":"https://openalex.org/keywords/dissipation","display_name":"Dissipation","score":0.4647819995880127},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4394950270652771},{"id":"https://openalex.org/keywords/linear-programming","display_name":"Linear programming","score":0.43364909291267395},{"id":"https://openalex.org/keywords/footprint","display_name":"Footprint","score":0.4132886826992035},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.371015340089798},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3351304531097412},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3141491711139679},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.27144724130630493},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2543640732765198},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.22887879610061646},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.22607919573783875},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11741670966148376}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.958939254283905},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.6303945183753967},{"id":"https://openalex.org/C56086750","wikidata":"https://www.wikidata.org/wiki/Q6042592","display_name":"Integer programming","level":2,"score":0.6170469522476196},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6166098713874817},{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.5957371592521667},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5020647048950195},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4855892062187195},{"id":"https://openalex.org/C2221639","wikidata":"https://www.wikidata.org/wiki/Q2877","display_name":"Discrete cosine transform","level":3,"score":0.4827924966812134},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.4647819995880127},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4394950270652771},{"id":"https://openalex.org/C41045048","wikidata":"https://www.wikidata.org/wiki/Q202843","display_name":"Linear programming","level":2,"score":0.43364909291267395},{"id":"https://openalex.org/C132943942","wikidata":"https://www.wikidata.org/wiki/Q2562511","display_name":"Footprint","level":2,"score":0.4132886826992035},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.371015340089798},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3351304531097412},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3141491711139679},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.27144724130630493},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2543640732765198},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.22887879610061646},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.22607919573783875},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11741670966148376},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2016.7538954","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2016.7538954","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.41999998688697815,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1483072402","https://openalex.org/W1968609578","https://openalex.org/W2008952711","https://openalex.org/W2016460235","https://openalex.org/W2037311165","https://openalex.org/W2042006644","https://openalex.org/W2052075409","https://openalex.org/W2057612354","https://openalex.org/W2081541784","https://openalex.org/W2111423786","https://openalex.org/W2119052406","https://openalex.org/W2139109474","https://openalex.org/W2153836091","https://openalex.org/W2156617155","https://openalex.org/W2159493595","https://openalex.org/W2160393392","https://openalex.org/W2295370265","https://openalex.org/W6682548619"],"related_works":["https://openalex.org/W2105974726","https://openalex.org/W1903431847","https://openalex.org/W2804025759","https://openalex.org/W1570136540","https://openalex.org/W2166021916","https://openalex.org/W1839177134","https://openalex.org/W2004001588","https://openalex.org/W2135482679","https://openalex.org/W2084005807","https://openalex.org/W1994884893"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"an":[3],"extended":[4,60],"Finite":[5],"State":[6],"Machine":[7],"with":[8,20,35],"Datapath":[9],"(FSMD)":[10],"partitioning":[11,45,62],"that":[12],"performs":[13],"three-dimensional":[14],"(3D)":[15],"high":[16],"level":[17],"synthesis":[18],"(HLS)":[19],"objectives":[21],"to":[22,30,39,71,99],"minimize":[23,72],"the":[24,32,101,104],"number":[25,81,110],"of":[26,76,82,103,109,111],"through-silicon-via":[27],"(TSV)":[28],"and":[29,53,85,113,122],"equip":[31],"synthesized":[33],"system":[34,52],"power":[36,79,114,117],"gating":[37,118],"capability":[38,119],"save":[40],"power.":[41],"The":[42],"original":[43],"FSMD":[44,61],"was":[46,54],"proposed":[47,105],"for":[48],"conventional":[49],"low-power":[50],"2D":[51],"only":[55],"employed":[56],"before":[57],"HLS.":[58],"Our":[59],"problem":[63],"is":[64,120],"formulated":[65],"using":[66],"integer":[67],"linear":[68],"programming":[69],"(ILP)":[70],"TSVs":[73,112],"under":[74],"constraints":[75],"footprint":[77],"area,":[78],"limit,":[80],"die":[83],"stacks":[84],"HLS":[86],"rules.":[87],"Case":[88],"study":[89],"has":[90],"been":[91],"conducted":[92],"on":[93],"Discrete":[94],"Cosine":[95],"Transform":[96],"(DCT)":[97],"circuit":[98],"evaluate":[100],"effectiveness":[102],"method":[106],"in":[107],"terms":[108],"dissipation.":[115],"Besides,":[116],"verified":[121],"analyzed.":[123]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":3},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}