{"id":"https://openalex.org/W2518628540","doi":"https://doi.org/10.1109/iscas.2016.7538916","title":"Time-mode techniques for fast-locking phase-locked loops","display_name":"Time-mode techniques for fast-locking phase-locked loops","publication_year":2016,"publication_date":"2016-05-01","ids":{"openalex":"https://openalex.org/W2518628540","doi":"https://doi.org/10.1109/iscas.2016.7538916","mag":"2518628540"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2016.7538916","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2016.7538916","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067922746","display_name":"Durand Jarrett-Amor","orcid":"https://orcid.org/0000-0003-3162-3422"},"institutions":[{"id":"https://openalex.org/I530967","display_name":"Toronto Metropolitan University","ror":"https://ror.org/05g13zd79","country_code":"CA","type":"education","lineage":["https://openalex.org/I530967"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Durand Jarrett-Amor","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Ryerson University, Toronto, ON, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Ryerson University, Toronto, ON, Canada","institution_ids":["https://openalex.org/I530967"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101852631","display_name":"Young Jun Park","orcid":"https://orcid.org/0000-0002-1461-5597"},"institutions":[{"id":"https://openalex.org/I530967","display_name":"Toronto Metropolitan University","ror":"https://ror.org/05g13zd79","country_code":"CA","type":"education","lineage":["https://openalex.org/I530967"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Young Jun Park","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Ryerson University, Toronto, ON, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Ryerson University, Toronto, ON, Canada","institution_ids":["https://openalex.org/I530967"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100698597","display_name":"Fei Yuan","orcid":"https://orcid.org/0000-0001-7758-5455"},"institutions":[{"id":"https://openalex.org/I530967","display_name":"Toronto Metropolitan University","ror":"https://ror.org/05g13zd79","country_code":"CA","type":"education","lineage":["https://openalex.org/I530967"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Fei Yuan","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Ryerson University, Toronto, ON, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Ryerson University, Toronto, ON, Canada","institution_ids":["https://openalex.org/I530967"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.08433048,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1790","last_page":"1793"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9962999820709229,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.9066203832626343},{"id":"https://openalex.org/keywords/voltage-controlled-oscillator","display_name":"Voltage-controlled oscillator","score":0.7634587287902832},{"id":"https://openalex.org/keywords/pll-multibit","display_name":"PLL multibit","score":0.6866428256034851},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.5379024744033813},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.5218631029129028},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5149258375167847},{"id":"https://openalex.org/keywords/charge-pump","display_name":"Charge pump","score":0.49733927845954895},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4625598192214966},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.4578910768032074},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4352886378765106},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.4172958433628082},{"id":"https://openalex.org/keywords/delay-locked-loop","display_name":"Delay-locked loop","score":0.4145088195800781},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.32176607847213745},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.31827759742736816},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.3022730350494385},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.24274498224258423},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2066003382205963},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.1351010799407959},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09168034791946411}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.9066203832626343},{"id":"https://openalex.org/C5291336","wikidata":"https://www.wikidata.org/wiki/Q852341","display_name":"Voltage-controlled oscillator","level":3,"score":0.7634587287902832},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.6866428256034851},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.5379024744033813},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.5218631029129028},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5149258375167847},{"id":"https://openalex.org/C114825011","wikidata":"https://www.wikidata.org/wiki/Q440704","display_name":"Charge pump","level":4,"score":0.49733927845954895},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4625598192214966},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.4578910768032074},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4352886378765106},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.4172958433628082},{"id":"https://openalex.org/C190462668","wikidata":"https://www.wikidata.org/wiki/Q492265","display_name":"Delay-locked loop","level":4,"score":0.4145088195800781},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.32176607847213745},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.31827759742736816},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.3022730350494385},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.24274498224258423},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2066003382205963},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.1351010799407959},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09168034791946411},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2016.7538916","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2016.7538916","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.9100000262260437,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1973902586","https://openalex.org/W2001276090","https://openalex.org/W2034517250","https://openalex.org/W2034525900","https://openalex.org/W2042668885","https://openalex.org/W2053596333","https://openalex.org/W2103900933","https://openalex.org/W2123352527","https://openalex.org/W2124140800","https://openalex.org/W2127893475","https://openalex.org/W2134713152","https://openalex.org/W2135906459","https://openalex.org/W2166268103","https://openalex.org/W6679055260"],"related_works":["https://openalex.org/W1486070987","https://openalex.org/W2217043549","https://openalex.org/W2087564251","https://openalex.org/W2369807905","https://openalex.org/W2752021769","https://openalex.org/W1600405202","https://openalex.org/W2339860780","https://openalex.org/W2401743820","https://openalex.org/W2976219355","https://openalex.org/W4385624389"],"abstract_inverted_index":{"A":[0],"fast-locking":[1],"phase-locked":[2],"loop":[3,7,87,103],"(PLL)":[4],"with":[5,18,148,174,201,224],"variable":[6,20],"dynamics":[8],"is":[9,204,210,227,233],"proposed.":[10],"The":[11,75,111],"PLL":[12,49,64,200,223],"employs":[13],"a":[14,19],"time":[15,83,197,220],"amplifier":[16],"(TA)":[17],"gain":[21],"to":[22,53,68],"amplify":[23],"the":[24,28,32,35,45,48,60,63,70,73,78,82,86,94,97,102,121,124,127,132,136,141,149,152,191,195,199,202,214,218,222,225],"phase":[25],"difference":[26],"between":[27],"reference":[29],"clock":[30],"and":[31,58,99,108,116,151,166,181],"output":[33],"of":[34,47,62,72,77,85,96,101,114,123,126,135,198,221],"voltage":[36,138],"controlled":[37],"oscillator":[38],"(VCO).":[39],"It":[40],"operates":[41],"by":[42],"dynamically":[43],"increasing":[44],"bandwidth":[46,61],"during":[50],"locking":[51,56],"state":[52,67],"speed":[54],"up":[55],"process":[57],"decreasing":[59],"in":[65,157,190],"locked":[66],"optimize":[69],"performance":[71],"PLL.":[74],"insertion":[76],"TA":[79,150,203,226],"also":[80,119],"reduces":[81],"constant":[84],"filter":[88,104],"without":[89,154,209,232],"sacrificing":[90],"performance,":[91],"thereby":[92,139],"allowing":[93],"reduction":[95,122],"resistance":[98],"capacitance":[100],"subsequently":[105],"their":[106],"silicon":[107],"power":[109,142],"consumption.":[110,143],"increased":[112],"width":[113],"Up":[115],"Down":[117],"pulses":[118],"enable":[120],"current":[125],"charge":[128],"pump":[129],"while":[130,207,230],"achieving":[131],"same":[133],"variation":[134],"control":[137],"lowering":[140],"Two":[144],"identical":[145],"PLLs,":[146],"one":[147],"other":[153],"were":[155,184],"designed":[156],"an":[158],"IBM":[159],"0.13":[160],"\u03bcm":[161],"CMOS":[162],"1.2":[163],"V":[164],"technology":[165],"analyzed":[167],"using":[168],"SpectreRF":[169],"from":[170],"Cadence":[171],"Design":[172],"Systems":[173],"BSIM4":[175],"device":[176],"models.":[177],"Both":[178],"critically":[179,192],"damped":[180,193,216],"under-damped":[182],"cases":[183],"investigated.":[185],"Simulation":[186],"results":[187],"demonstrate":[188],"that":[189,208,231],"case,":[194,217],"lock":[196,219],"0.42":[205],"\u03bcs":[206,229],"0.52":[211],"\u03bcs.":[212,235],"In":[213],"under":[215],"0.30":[228],"1.54":[234]},"counts_by_year":[{"year":2021,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
