{"id":"https://openalex.org/W2516614064","doi":"https://doi.org/10.1109/iscas.2016.7527337","title":"A reduced hardware complexity data-weighted averaging algorithm with no tonal behavior","display_name":"A reduced hardware complexity data-weighted averaging algorithm with no tonal behavior","publication_year":2016,"publication_date":"2016-05-01","ids":{"openalex":"https://openalex.org/W2516614064","doi":"https://doi.org/10.1109/iscas.2016.7527337","mag":"2516614064"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2016.7527337","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2016.7527337","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5024345103","display_name":"Alberto Celin","orcid":null},"institutions":[{"id":"https://openalex.org/I138689650","display_name":"University of Padua","ror":"https://ror.org/00240q980","country_code":"IT","type":"education","lineage":["https://openalex.org/I138689650"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Alberto Celin","raw_affiliation_strings":["Department of Information Engineering, University of Padova, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Information Engineering, University of Padova, Italy","institution_ids":["https://openalex.org/I138689650"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5047727757","display_name":"Andrea Gerosa","orcid":"https://orcid.org/0000-0002-3395-8034"},"institutions":[{"id":"https://openalex.org/I138689650","display_name":"University of Padua","ror":"https://ror.org/00240q980","country_code":"IT","type":"education","lineage":["https://openalex.org/I138689650"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Andrea Gerosa","raw_affiliation_strings":["Department of Information Engineering, University of Padova, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Information Engineering, University of Padova, Italy","institution_ids":["https://openalex.org/I138689650"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I138689650"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.08883581,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"37","issue":null,"first_page":"702","last_page":"705"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/oversampling","display_name":"Oversampling","score":0.7902090549468994},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6458771228790283},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.6187514066696167},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5975826382637024},{"id":"https://openalex.org/keywords/linearity","display_name":"Linearity","score":0.5553966164588928},{"id":"https://openalex.org/keywords/converters","display_name":"Converters","score":0.5505316257476807},{"id":"https://openalex.org/keywords/delta-sigma-modulation","display_name":"Delta-sigma modulation","score":0.5314575433731079},{"id":"https://openalex.org/keywords/spurious-relationship","display_name":"Spurious relationship","score":0.5119946599006653},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.4455808997154236},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.43298637866973877},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3489200472831726},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3271210491657257},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14939984679222107},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.12766581773757935}],"concepts":[{"id":"https://openalex.org/C197323446","wikidata":"https://www.wikidata.org/wiki/Q331222","display_name":"Oversampling","level":3,"score":0.7902090549468994},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6458771228790283},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.6187514066696167},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5975826382637024},{"id":"https://openalex.org/C77170095","wikidata":"https://www.wikidata.org/wiki/Q1753188","display_name":"Linearity","level":2,"score":0.5553966164588928},{"id":"https://openalex.org/C2778422915","wikidata":"https://www.wikidata.org/wiki/Q10302051","display_name":"Converters","level":3,"score":0.5505316257476807},{"id":"https://openalex.org/C68754193","wikidata":"https://www.wikidata.org/wiki/Q1184820","display_name":"Delta-sigma modulation","level":3,"score":0.5314575433731079},{"id":"https://openalex.org/C97256817","wikidata":"https://www.wikidata.org/wiki/Q1462316","display_name":"Spurious relationship","level":2,"score":0.5119946599006653},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.4455808997154236},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.43298637866973877},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3489200472831726},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3271210491657257},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14939984679222107},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.12766581773757935},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2016.7527337","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2016.7527337","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},{"id":"pmh:oai:www.research.unipd.it:11577/3247456","is_oa":false,"landing_page_url":"http://hdl.handle.net/11577/3247456","pdf_url":null,"source":{"id":"https://openalex.org/S4306402547","display_name":"Padua Research Archive (University of Padova)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I138689650","host_organization_name":"University of Padua","host_organization_lineage":["https://openalex.org/I138689650"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1509148781","https://openalex.org/W1973196985","https://openalex.org/W1991657939","https://openalex.org/W2012846466","https://openalex.org/W2082670617","https://openalex.org/W2113192550","https://openalex.org/W2154694501","https://openalex.org/W2160829086","https://openalex.org/W2166948256","https://openalex.org/W6648297562"],"related_works":["https://openalex.org/W2040229502","https://openalex.org/W1580014081","https://openalex.org/W2421111280","https://openalex.org/W2097165798","https://openalex.org/W1497881430","https://openalex.org/W2599174517","https://openalex.org/W2117483815","https://openalex.org/W2170102475","https://openalex.org/W3175904419","https://openalex.org/W2545192519"],"abstract_inverted_index":{"Data-weighted":[0],"averaging":[1,81],"is":[2,26,40],"a":[3,36,77,107],"widely":[4],"used":[5],"approach":[6],"to":[7,18,50,58,69],"cancel":[8],"the":[9,24,28,43,70,92,96,103,124,128],"non":[10],"linearity":[11],"arising":[12],"from":[13],"device":[14],"mismatch":[15],"in":[16,27,42,106],"digital":[17],"analog":[19],"converters":[20],"(DAC),":[21],"especially":[22],"when":[23,35],"DAC":[25],"feedback":[29],"path":[30],"of":[31,95,119],"Sigma-Delta":[32],"modulators.":[33],"However,":[34],"low":[37],"oversampling":[38],"ratio":[39],"assumed":[41],"modulator,":[44],"spurious":[45],"tone":[46],"can":[47],"arise":[48],"due":[49],"algorithm":[51,113],"ciclicity.":[52],"The":[53,100,112],"literature":[54],"offers":[55],"some":[56],"solutions":[57],"such":[59],"an":[60],"issue,":[61],"which":[62],"however":[63],"often":[64],"become":[65],"critical":[66],"with":[67],"respect":[68],"corresponding":[71],"hardware":[72,93,104],"implementation.":[73],"This":[74],"paper":[75,101],"proposes":[76],"modified":[78],"bidirectional":[79],"data-weighted":[80,98],"algorithm,":[82],"whose":[83],"circuit":[84],"implementation":[85,105],"preserves":[86],"spurs":[87],"immunity,":[88],"while":[89],"it":[90],"equates":[91],"complexity":[94],"basic":[97],"algorithm.":[99],"reports":[102],"65":[108],"nm":[109],"CMOS":[110],"technology.":[111],"performances":[114],"are":[115],"assessed":[116],"by":[117],"means":[118],"exhaustive":[120],"simulations":[121],"both":[122],"at":[123,127],"transistor":[125],"and":[126],"system":[129],"level.":[130]},"counts_by_year":[],"updated_date":"2026-07-02T09:51:11.867554","created_date":"2025-10-10T00:00:00"}