{"id":"https://openalex.org/W2513740827","doi":"https://doi.org/10.1109/iscas.2016.7527233","title":"A compact spatially configurable differential input stage for a field programmable interconnection network","display_name":"A compact spatially configurable differential input stage for a field programmable interconnection network","publication_year":2016,"publication_date":"2016-05-01","ids":{"openalex":"https://openalex.org/W2513740827","doi":"https://doi.org/10.1109/iscas.2016.7527233","mag":"2513740827"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2016.7527233","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2016.7527233","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051704528","display_name":"Wasim Hussain","orcid":"https://orcid.org/0000-0003-0812-6276"},"institutions":[{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Wasim Hussain","raw_affiliation_strings":["Polytechnique Montr\u00e9al"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Polytechnique Montr\u00e9al","institution_ids":["https://openalex.org/I45683168"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038488044","display_name":"Yvon Savaria","orcid":"https://orcid.org/0000-0002-3404-9959"},"institutions":[{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Yvon Savaria","raw_affiliation_strings":["Polytechnique Montr\u00e9al"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Polytechnique Montr\u00e9al","institution_ids":["https://openalex.org/I45683168"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071840145","display_name":"Yves Blaqui\u00e8re","orcid":"https://orcid.org/0000-0001-6204-7427"},"institutions":[{"id":"https://openalex.org/I159129438","display_name":"Universit\u00e9 du Qu\u00e9bec \u00e0 Montr\u00e9al","ror":"https://ror.org/002rjbv21","country_code":"CA","type":"education","lineage":["https://openalex.org/I159129438","https://openalex.org/I49663120"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Yves Blaquiere","raw_affiliation_strings":["Universit\u00e9 du Qu\u00e9bec \u00e0 Montr\u00e9al (UQAM)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universit\u00e9 du Qu\u00e9bec \u00e0 Montr\u00e9al (UQAM)","institution_ids":["https://openalex.org/I159129438"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.08362485,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"313","last_page":"316"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7631232738494873},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.7401899099349976},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7095761895179749},{"id":"https://openalex.org/keywords/common-mode-signal","display_name":"Common-mode signal","score":0.6246544718742371},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5917020440101624},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.5782942175865173},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5325972437858582},{"id":"https://openalex.org/keywords/differential","display_name":"Differential (mechanical device)","score":0.5121450424194336},{"id":"https://openalex.org/keywords/multi-stage","display_name":"Multi stage","score":0.4531238377094269},{"id":"https://openalex.org/keywords/stage","display_name":"Stage (stratigraphy)","score":0.4345276355743408},{"id":"https://openalex.org/keywords/mode","display_name":"Mode (computer interface)","score":0.4206051826477051},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.3395484685897827},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3329690396785736},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3057815432548523},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.23004242777824402},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.21502330899238586},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19754844903945923},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1623857319355011},{"id":"https://openalex.org/keywords/analog-signal","display_name":"Analog signal","score":0.09226325154304504}],"concepts":[{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7631232738494873},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.7401899099349976},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7095761895179749},{"id":"https://openalex.org/C189714311","wikidata":"https://www.wikidata.org/wiki/Q1530371","display_name":"Common-mode signal","level":4,"score":0.6246544718742371},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5917020440101624},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5782942175865173},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5325972437858582},{"id":"https://openalex.org/C93226319","wikidata":"https://www.wikidata.org/wiki/Q193137","display_name":"Differential (mechanical device)","level":2,"score":0.5121450424194336},{"id":"https://openalex.org/C3017905481","wikidata":"https://www.wikidata.org/wiki/Q1161829","display_name":"Multi stage","level":2,"score":0.4531238377094269},{"id":"https://openalex.org/C146357865","wikidata":"https://www.wikidata.org/wiki/Q1123245","display_name":"Stage (stratigraphy)","level":2,"score":0.4345276355743408},{"id":"https://openalex.org/C48677424","wikidata":"https://www.wikidata.org/wiki/Q6888088","display_name":"Mode (computer interface)","level":2,"score":0.4206051826477051},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.3395484685897827},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3329690396785736},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3057815432548523},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.23004242777824402},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.21502330899238586},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19754844903945923},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1623857319355011},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.09226325154304504},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.0},{"id":"https://openalex.org/C21880701","wikidata":"https://www.wikidata.org/wiki/Q2144042","display_name":"Process engineering","level":1,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/iscas.2016.7527233","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2016.7527233","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},{"id":"pmh:oai:espace2.etsmtl.ca:25335","is_oa":false,"landing_page_url":"https://espace2.etsmtl.ca/id/eprint/25335/","pdf_url":null,"source":{"id":"https://openalex.org/S4306402392","display_name":"Espace \u00c9TS (ETS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1341030882","host_organization_name":"Educational Testing Service","host_organization_lineage":["https://openalex.org/I1341030882"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Compte rendu de conf\u00e9rence"},{"id":"pmh:oai:publications.polymtl.ca:35906","is_oa":false,"landing_page_url":"https://publications.polymtl.ca/35906/","pdf_url":null,"source":{"id":"https://openalex.org/S4306401013","display_name":"PolyPublie (\u00c9cole Polytechnique de Montr\u00e9al)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I45683168","host_organization_name":"Polytechnique Montr\u00e9al","host_organization_lineage":["https://openalex.org/I45683168"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Communication de conf\u00e9rence"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.5799999833106995,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2143896691","https://openalex.org/W2150245492","https://openalex.org/W2162221699"],"related_works":["https://openalex.org/W4323268213","https://openalex.org/W4242128654","https://openalex.org/W2152549830","https://openalex.org/W2039899645","https://openalex.org/W2371342700","https://openalex.org/W2327110311","https://openalex.org/W2363059241","https://openalex.org/W3215187042","https://openalex.org/W266342242","https://openalex.org/W2100439961"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,84,107],"spatially":[4],"configurable":[5],"input":[6,23,43,51,67,78,109],"stage":[7,24,52,79,110],"for":[8,29,65],"differential-to-single":[9,30],"ended":[10,17,31],"conversion":[11],"enabling":[12],"signal":[13],"propagation":[14],"through":[15],"single":[16],"field":[18],"programmable":[19],"interconnection":[20],"networks.":[21],"The":[22,77],"uses":[25],"current":[26],"mode":[27,36],"sensing":[28],"conversion.":[32],"Compared":[33],"to":[34,59],"voltage":[35,69],"sensing,":[37],"it":[38],"can":[39,53],"support":[40,54],"higher":[41],"common-mode":[42,68],"voltage.":[44],"Post-layout":[45],"Monte-Carlo":[46],"simulations":[47],"show":[48],"that":[49,94,104],"the":[50,95],"data":[55],"rates":[56],"of":[57,70],"up":[58],"2":[60],"Gbps":[61,64],"and":[62,73,90],"1":[63],"an":[66],"1.2-1.6":[71],"V":[72,75],"1.2-2.0":[74],"respectively.":[76],"was":[80],"laid":[81],"out":[82],"in":[83],"mature":[85],"0.13":[86],"\u03bcm":[87],"CMOS":[88],"technology":[89],"reported":[91],"results":[92],"demonstrate":[93],"occupied":[96],"silicon":[97],"area":[98],"is":[99],"22":[100],"times":[101],"smaller":[102],"than":[103],"required":[105],"by":[106],"differential":[108],"based":[111],"on":[112],"unity-gain":[113],"buffer":[114],"multiplexers.":[115]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}