{"id":"https://openalex.org/W2516725835","doi":"https://doi.org/10.1109/iscas.2016.7527157","title":"Coresidual alias-locked loops","display_name":"Coresidual alias-locked loops","publication_year":2016,"publication_date":"2016-05-01","ids":{"openalex":"https://openalex.org/W2516725835","doi":"https://doi.org/10.1109/iscas.2016.7527157","mag":"2516725835"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2016.7527157","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2016.7527157","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111719252","display_name":"Jinghang Liang","orcid":null},"institutions":[{"id":"https://openalex.org/I154425047","display_name":"University of Alberta","ror":"https://ror.org/0160cpw27","country_code":"CA","type":"education","lineage":["https://openalex.org/I154425047"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Jinghang Liang","raw_affiliation_strings":["[Department of ECE, University of Alberta, Edmonton, Alberta]"],"affiliations":[{"raw_affiliation_string":"[Department of ECE, University of Alberta, Edmonton, Alberta]","institution_ids":["https://openalex.org/I154425047"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5066973305","display_name":"D.G. Elliott","orcid":"https://orcid.org/0000-0003-0438-1800"},"institutions":[{"id":"https://openalex.org/I154425047","display_name":"University of Alberta","ror":"https://ror.org/0160cpw27","country_code":"CA","type":"education","lineage":["https://openalex.org/I154425047"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Duncan G. Elliott","raw_affiliation_strings":["[Department of ECE, University of Alberta, Edmonton, Alberta]"],"affiliations":[{"raw_affiliation_string":"[Department of ECE, University of Alberta, Edmonton, Alberta]","institution_ids":["https://openalex.org/I154425047"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5111719252"],"corresponding_institution_ids":["https://openalex.org/I154425047"],"apc_list":null,"apc_paid":null,"fwci":0.1838,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.57732023,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"1","issue":null,"first_page":"9","last_page":"12"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/alias","display_name":"Alias","score":0.8379243612289429},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5753198266029358},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.42329180240631104},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.1161825954914093},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08207163214683533},{"id":"https://openalex.org/keywords/database","display_name":"Database","score":0.0726022720336914}],"concepts":[{"id":"https://openalex.org/C46681722","wikidata":"https://www.wikidata.org/wiki/Q4725589","display_name":"Alias","level":2,"score":0.8379243612289429},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5753198266029358},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.42329180240631104},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.1161825954914093},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08207163214683533},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0726022720336914}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2016.7527157","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2016.7527157","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.800000011920929,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1500201982","https://openalex.org/W1569114084","https://openalex.org/W2088743615","https://openalex.org/W2105014900","https://openalex.org/W2160721146","https://openalex.org/W6633696140"],"related_works":["https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W4385605198","https://openalex.org/W4256550813","https://openalex.org/W2056017980","https://openalex.org/W2333004434","https://openalex.org/W2151266859","https://openalex.org/W1557487237","https://openalex.org/W275149381","https://openalex.org/W4386805122"],"abstract_inverted_index":{"A":[0],"coresidual":[1,119],"alias-locked":[2,19],"loop":[3,20],"(C-ALL)":[4],"introduces":[5],"a":[6,29,38,115,118],"technique":[7],"to":[8,60,89,93,111],"reduce":[9,138],"spurs":[10,66],"in":[11,35,103,123],"the":[12,50,61,68,74,78,90,96,104,108,112,128],"voltage-controlled":[13],"oscillator":[14],"(VCO)":[15],"output":[16,23,139],"of":[17,24,41,49,55,57,81],"an":[18,25,46],"(ALL).":[21],"The":[22,53,71,98],"ALL":[26],"subsampler":[27],"provides":[28,86],"digital":[30,105],"aliased":[31],"frequency,":[32],"that":[33,127],"when":[34],"lock,":[36],"is":[37,101],"recurring":[39],"sequence":[40],"1's":[42,82],"and":[43,83,85],"0's":[44,84],"at":[45],"average":[47],"frequency":[48],"reference":[51,62,109],"clock.":[52],"lack":[54],"alignment":[56],"this":[58,87],"bitstream":[59],"clock":[63],"can":[64,131],"produce":[65],"on":[67],"VCO":[69],"output.":[70],"C-ALL":[72,116],"solves":[73],"problem":[75],"by":[76,141],"predicting":[77],"expected":[79,99],"pattern":[80,100],"signal":[88,110],"phase":[91],"detector":[92],"compare":[94],"with":[95],"subsampler.":[97],"generated":[102],"domain":[106],"as":[107],"PFD,":[113],"therefore":[114],"implements":[117],"function.":[120],"Functional":[121],"simulation":[122],"Spectre":[124],"has":[125],"verified":[126],"proposed":[129],"design":[130],"not":[132],"only":[133],"achieve":[134],"lock":[135],"but":[136],"also":[137],"spur":[140],"34.82":[142],"dBc.":[143]},"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}