{"id":"https://openalex.org/W1544954279","doi":"https://doi.org/10.1109/iscas.2015.7169216","title":"Power optimization design for probabilistic logic circuits","display_name":"Power optimization design for probabilistic logic circuits","publication_year":2015,"publication_date":"2015-05-01","ids":{"openalex":"https://openalex.org/W1544954279","doi":"https://doi.org/10.1109/iscas.2015.7169216","mag":"1544954279"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2015.7169216","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2015.7169216","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101802228","display_name":"Ran Xiao","orcid":"https://orcid.org/0000-0002-0918-0533"},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"education","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Ran Xiao","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Windsor, Ontario, Canada","Department of Electrical and Computer Engineering,University of Windsor,Ontario,Canada N9B 3P4)"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Windsor, Ontario, Canada","institution_ids":["https://openalex.org/I74413500"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering,University of Windsor,Ontario,Canada N9B 3P4)","institution_ids":["https://openalex.org/I74413500"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101827210","display_name":"Chunhong Chen","orcid":"https://orcid.org/0000-0001-7934-7725"},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"education","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Chunhong Chen","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Windsor, Ontario, Canada","Department of Electrical and Computer Engineering,University of Windsor,Ontario,Canada N9B 3P4)"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Windsor, Ontario, Canada","institution_ids":["https://openalex.org/I74413500"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering,University of Windsor,Ontario,Canada N9B 3P4)","institution_ids":["https://openalex.org/I74413500"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5101802228"],"corresponding_institution_ids":["https://openalex.org/I74413500"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.02494265,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"2593","last_page":"2595"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9952999949455261,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/probabilistic-logic","display_name":"Probabilistic logic","score":0.8020395636558533},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6549792289733887},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6157466769218445},{"id":"https://openalex.org/keywords/power-optimization","display_name":"Power optimization","score":0.5970337390899658},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.5936387181282043},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5244819521903992},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5168231129646301},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.47751322388648987},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.4607997238636017},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4393366873264313},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.43869736790657043},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.41909411549568176},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.33185815811157227},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.32747840881347656},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.23930108547210693},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17909592390060425},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.168873131275177},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.15669137239456177},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.11529648303985596},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.07825925946235657}],"concepts":[{"id":"https://openalex.org/C49937458","wikidata":"https://www.wikidata.org/wiki/Q2599292","display_name":"Probabilistic logic","level":2,"score":0.8020395636558533},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6549792289733887},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6157466769218445},{"id":"https://openalex.org/C168292644","wikidata":"https://www.wikidata.org/wiki/Q10860336","display_name":"Power optimization","level":4,"score":0.5970337390899658},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.5936387181282043},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5244819521903992},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5168231129646301},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.47751322388648987},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.4607997238636017},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4393366873264313},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.43869736790657043},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.41909411549568176},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.33185815811157227},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.32747840881347656},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.23930108547210693},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17909592390060425},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.168873131275177},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.15669137239456177},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.11529648303985596},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.07825925946235657},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2015.7169216","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2015.7169216","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1998921161","https://openalex.org/W2035974948","https://openalex.org/W2068710123","https://openalex.org/W2133406150","https://openalex.org/W2143674663","https://openalex.org/W2143727636","https://openalex.org/W2167037406","https://openalex.org/W3144286968","https://openalex.org/W3145958020"],"related_works":["https://openalex.org/W2098419840","https://openalex.org/W1966764473","https://openalex.org/W2789349722","https://openalex.org/W1985308002","https://openalex.org/W2056896932","https://openalex.org/W2614722573","https://openalex.org/W2121963733","https://openalex.org/W1977171228","https://openalex.org/W2059422871","https://openalex.org/W2041787842"],"abstract_inverted_index":{"With":[0],"CMOS":[1],"technology":[2],"approaching":[3],"the":[4,14,37,59,72],"nanometer":[5],"scale,":[6],"probabilistic":[7,27],"design":[8,48],"has":[9],"received":[10],"much":[11],"attention":[12],"from":[13],"research":[15],"community.":[16],"In":[17],"this":[18],"paper,":[19],"we":[20],"propose":[21],"a":[22,80,92],"power":[23,51,60,89],"optimization":[24],"methodology":[25],"for":[26,50],"logic":[28],"circuits":[29,35,63],"with":[30,47],"stochastic":[31],"components.":[32],"Inexactness":[33],"in":[34,86],"allows":[36],"local":[38],"reliability-power":[39],"tradeoff":[40],"of":[41,62,82,88],"unreliable":[42],"components,":[43],"and":[44],"provides":[45],"us":[46],"space":[49],"optimization.":[52],"The":[53],"proposed":[54,73],"approach":[55],"aims":[56],"to":[57],"minimize":[58],"cost":[61],"under":[64,91],"certain":[65],"error":[66,95],"rate":[67],"constraints.":[68],"We":[69],"show":[70],"that":[71],"method":[74],"outperforms":[75],"other":[76],"intuitive":[77],"approaches":[78],"by":[79],"factor":[81],"2.5X,":[83],"on":[84],"average,":[85],"terms":[87],"costs":[90],"same":[93],"target":[94],"rate.":[96]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
