{"id":"https://openalex.org/W1510452813","doi":"https://doi.org/10.1109/iscas.2015.7169205","title":"A 28nm 36kb high speed 6T SRAM with source follower PMOS read and bit-line under-drive","display_name":"A 28nm 36kb high speed 6T SRAM with source follower PMOS read and bit-line under-drive","publication_year":2015,"publication_date":"2015-05-01","ids":{"openalex":"https://openalex.org/W1510452813","doi":"https://doi.org/10.1109/iscas.2015.7169205","mag":"1510452813"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2015.7169205","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2015.7169205","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5011840601","display_name":"Chi-Hao Hong","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Chi-Hao Hong","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C","[Department of Electronics Engineering, National Chiao Tung University, HsinChu, Taiwan, R.O.C.]"],"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"[Department of Electronics Engineering, National Chiao Tung University, HsinChu, Taiwan, R.O.C.]","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111075902","display_name":"Yi-Wei Chiu","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yi-Wei Chiu","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C","[Department of Electronics Engineering, National Chiao Tung University, HsinChu, Taiwan, R.O.C.]"],"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"[Department of Electronics Engineering, National Chiao Tung University, HsinChu, Taiwan, R.O.C.]","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101728083","display_name":"Junkai Zhao","orcid":"https://orcid.org/0000-0001-9901-4338"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jun-Kai Zhao","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C","[Department of Electronics Engineering, National Chiao Tung University, HsinChu, Taiwan, R.O.C.]"],"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"[Department of Electronics Engineering, National Chiao Tung University, HsinChu, Taiwan, R.O.C.]","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061859062","display_name":"Shyh\u2010Jye Jou","orcid":"https://orcid.org/0000-0002-8821-3486"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Shyh-Jye Jou","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C","[Department of Electronics Engineering, National Chiao Tung University, HsinChu, Taiwan, R.O.C.]"],"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"[Department of Electronics Engineering, National Chiao Tung University, HsinChu, Taiwan, R.O.C.]","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073775550","display_name":"Wen-Tai Wang","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Wen-Tai Wang","raw_affiliation_strings":["Global Unichip Corporation (GUC), Hsinchu, Taiwan, R.O.C"],"affiliations":[{"raw_affiliation_string":"Global Unichip Corporation (GUC), Hsinchu, Taiwan, R.O.C","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5062011620","display_name":"Reed Lee","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Reed Lee","raw_affiliation_strings":["Global Unichip Corporation (GUC), Hsinchu, Taiwan, R.O.C"],"affiliations":[{"raw_affiliation_string":"Global Unichip Corporation (GUC), Hsinchu, Taiwan, R.O.C","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5011840601"],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.01951805,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"2549","last_page":"2552"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.9636293649673462},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.9157339334487915},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.6690114140510559},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5551763772964478},{"id":"https://openalex.org/keywords/line","display_name":"Line (geometry)","score":0.47622090578079224},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4590406119823456},{"id":"https://openalex.org/keywords/access-time","display_name":"Access time","score":0.4480496048927307},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.4113542437553406},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.4110395312309265},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.40436869859695435},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.37747523188591003},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3493788242340088},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.32459554076194763},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.2632424533367157},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23869886994361877},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.052119553089141846}],"concepts":[{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.9636293649673462},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.9157339334487915},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.6690114140510559},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5551763772964478},{"id":"https://openalex.org/C198352243","wikidata":"https://www.wikidata.org/wiki/Q37105","display_name":"Line (geometry)","level":2,"score":0.47622090578079224},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4590406119823456},{"id":"https://openalex.org/C194080101","wikidata":"https://www.wikidata.org/wiki/Q46306","display_name":"Access time","level":2,"score":0.4480496048927307},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.4113542437553406},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.4110395312309265},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.40436869859695435},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.37747523188591003},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3493788242340088},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.32459554076194763},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.2632424533367157},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23869886994361877},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.052119553089141846},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2015.7169205","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2015.7169205","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8700000047683716,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1979394618","https://openalex.org/W2008870315","https://openalex.org/W2045074698","https://openalex.org/W2077354460","https://openalex.org/W2078301093","https://openalex.org/W2095913060","https://openalex.org/W2152506767","https://openalex.org/W2162154752","https://openalex.org/W2165720303","https://openalex.org/W4244763807"],"related_works":["https://openalex.org/W4386261925","https://openalex.org/W2082944690","https://openalex.org/W2263373136","https://openalex.org/W2023334077","https://openalex.org/W2005494397","https://openalex.org/W1811213809","https://openalex.org/W1914349328","https://openalex.org/W2160067645","https://openalex.org/W2339836056","https://openalex.org/W3192888672"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3,56],"present":[4,21],"source":[5,26,132],"follower":[6,27,133],"PMOS":[7,28,134],"Read":[8,135],"and":[9,136],"bit-line":[10,59,137],"under-drive":[11,60,138],"techniques":[12,139],"to":[13,20,31,36,54,62,92],"improve":[14,48],"the":[15,49,64,74,93,104,107,111,151,157],"operation":[16],"speed":[17,127],"as":[18],"compared":[19,91],"commercial":[22,100,121],"SRAM":[23,94,101,113,122,129,159],"compilers.":[24,123],"A":[25,124],"is":[29,77,97,115,140],"utilized":[30],"connect":[32],"local":[33],"bit-lines":[34,38],"(LBL)":[35],"global":[37],"(GBL)":[39],"instead":[40],"of":[41,67,73,110,120,150],"using":[42],"a":[43,58],"NAND":[44],"gate.":[45],"To":[46],"further":[47],"discharging":[50],"time":[51,72,109],"from":[52],"LBL":[53],"GBL,":[55],"propose":[57],"circuit":[61],"reduce":[63],"voltage":[65],"level":[66],"LBL.":[68],"The":[69,147],"simulated":[70],"access":[71,108],"proposed":[75,112,158],"macro":[76,95,114,160],"445":[78],"ps":[79],"at":[80,165,168],"slow":[81,83],"N":[82],"P":[84],"(SS)":[85],"corner,":[86],"-40\u00b0C,":[87],"0.81":[88,169],"V.":[89],"As":[90],"which":[96],"generated":[98],"by":[99],"compilers":[102],"with":[103,131],"fastest":[105],"combination,":[106],"12%":[116],"faster":[117],"than":[118],"that":[119],"36kb":[125],"high":[126],"6T":[128],"macros":[130],"fabricated":[141],"in":[142,153],"28nm":[143],"HKMG":[144],"CMOS":[145],"process.":[146],"measurement":[148],"results":[149],"chip":[152],"SS":[154],"corner":[155],"show":[156],"passes":[161],"all":[162],"MBIST":[163],"patterns":[164],"500":[166],"MHz":[167],"V,":[170],"room":[171],"temperature.":[172]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
