{"id":"https://openalex.org/W1487631000","doi":"https://doi.org/10.1109/iscas.2015.7169014","title":"A study for replacing CMOS gates by equivalent inverters","display_name":"A study for replacing CMOS gates by equivalent inverters","publication_year":2015,"publication_date":"2015-05-01","ids":{"openalex":"https://openalex.org/W1487631000","doi":"https://doi.org/10.1109/iscas.2015.7169014","mag":"1487631000"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2015.7169014","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2015.7169014","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064140006","display_name":"Ch. Galani","orcid":null},"institutions":[{"id":"https://openalex.org/I21370196","display_name":"Aristotle University of Thessaloniki","ror":"https://ror.org/02j61yw88","country_code":"GR","type":"education","lineage":["https://openalex.org/I21370196"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Ch. Galani","raw_affiliation_strings":["Department of Physics Aristotle, University of Thessaloniki, Thessaloniki, Greece","Department of Physics, Aristotle University of Thessaloniki, 54124\u2005Thessaloniki, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Physics Aristotle, University of Thessaloniki, Thessaloniki, Greece","institution_ids":["https://openalex.org/I21370196"]},{"raw_affiliation_string":"Department of Physics, Aristotle University of Thessaloniki, 54124\u2005Thessaloniki, Greece","institution_ids":["https://openalex.org/I21370196"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016760353","display_name":"A. Tsormpatzoglou","orcid":"https://orcid.org/0009-0004-9182-778X"},"institutions":[{"id":"https://openalex.org/I21370196","display_name":"Aristotle University of Thessaloniki","ror":"https://ror.org/02j61yw88","country_code":"GR","type":"education","lineage":["https://openalex.org/I21370196"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"A. Tsormpatzoglou","raw_affiliation_strings":["Department of Physics Aristotle, University of Thessaloniki, Thessaloniki, Greece","Department of Physics, Aristotle University of Thessaloniki, 54124\u2005Thessaloniki, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Physics Aristotle, University of Thessaloniki, Thessaloniki, Greece","institution_ids":["https://openalex.org/I21370196"]},{"raw_affiliation_string":"Department of Physics, Aristotle University of Thessaloniki, 54124\u2005Thessaloniki, Greece","institution_ids":["https://openalex.org/I21370196"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069176937","display_name":"Panagiotis Chaourani","orcid":"https://orcid.org/0000-0002-7534-9317"},"institutions":[{"id":"https://openalex.org/I21370196","display_name":"Aristotle University of Thessaloniki","ror":"https://ror.org/02j61yw88","country_code":"GR","type":"education","lineage":["https://openalex.org/I21370196"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"P. Chaourani","raw_affiliation_strings":["Department of Physics Aristotle, University of Thessaloniki, Thessaloniki, Greece","Department of Physics, Aristotle University of Thessaloniki, 54124\u2005Thessaloniki, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Physics Aristotle, University of Thessaloniki, Thessaloniki, Greece","institution_ids":["https://openalex.org/I21370196"]},{"raw_affiliation_string":"Department of Physics, Aristotle University of Thessaloniki, 54124\u2005Thessaloniki, Greece","institution_ids":["https://openalex.org/I21370196"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004169838","display_name":"Ioannis Messaris","orcid":"https://orcid.org/0000-0002-4286-6553"},"institutions":[{"id":"https://openalex.org/I21370196","display_name":"Aristotle University of Thessaloniki","ror":"https://ror.org/02j61yw88","country_code":"GR","type":"education","lineage":["https://openalex.org/I21370196"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"I. Messaris","raw_affiliation_strings":["Department of Physics Aristotle, University of Thessaloniki, Thessaloniki, Greece","Department of Physics, Aristotle University of Thessaloniki, 54124\u2005Thessaloniki, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Physics Aristotle, University of Thessaloniki, Thessaloniki, Greece","institution_ids":["https://openalex.org/I21370196"]},{"raw_affiliation_string":"Department of Physics, Aristotle University of Thessaloniki, 54124\u2005Thessaloniki, Greece","institution_ids":["https://openalex.org/I21370196"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5023894427","display_name":"S. Nikolaidis","orcid":"https://orcid.org/0000-0002-9794-8062"},"institutions":[{"id":"https://openalex.org/I21370196","display_name":"Aristotle University of Thessaloniki","ror":"https://ror.org/02j61yw88","country_code":"GR","type":"education","lineage":["https://openalex.org/I21370196"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"S. Nikolaidis","raw_affiliation_strings":["Department of Physics Aristotle, University of Thessaloniki, Thessaloniki, Greece","Department of Physics, Aristotle University of Thessaloniki, 54124\u2005Thessaloniki, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Physics Aristotle, University of Thessaloniki, Thessaloniki, Greece","institution_ids":["https://openalex.org/I21370196"]},{"raw_affiliation_string":"Department of Physics, Aristotle University of Thessaloniki, 54124\u2005Thessaloniki, Greece","institution_ids":["https://openalex.org/I21370196"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I21370196"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1838","last_page":"1841"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.8251876831054688},{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.8229759335517883},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7661187052726746},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.6348760724067688},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6297236680984497},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6038414835929871},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5213626623153687},{"id":"https://openalex.org/keywords/gate-equivalent","display_name":"Gate equivalent","score":0.508470892906189},{"id":"https://openalex.org/keywords/parametric-statistics","display_name":"Parametric statistics","score":0.4959507882595062},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4714547097682953},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.45073169469833374},{"id":"https://openalex.org/keywords/nand-logic","display_name":"NAND logic","score":0.4455844461917877},{"id":"https://openalex.org/keywords/nor-gate","display_name":"NOR gate","score":0.4365110993385315},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.37441468238830566},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3631182909011841},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3215790390968323},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2884587049484253},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.24174648523330688},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.17249217629432678},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.15362629294395447},{"id":"https://openalex.org/keywords/gate-oxide","display_name":"Gate oxide","score":0.1165216863155365}],"concepts":[{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.8251876831054688},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.8229759335517883},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7661187052726746},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.6348760724067688},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6297236680984497},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6038414835929871},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5213626623153687},{"id":"https://openalex.org/C60697091","wikidata":"https://www.wikidata.org/wiki/Q5527009","display_name":"Gate equivalent","level":5,"score":0.508470892906189},{"id":"https://openalex.org/C117251300","wikidata":"https://www.wikidata.org/wiki/Q1849855","display_name":"Parametric statistics","level":2,"score":0.4959507882595062},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4714547097682953},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.45073169469833374},{"id":"https://openalex.org/C7234692","wikidata":"https://www.wikidata.org/wiki/Q4116068","display_name":"NAND logic","level":4,"score":0.4455844461917877},{"id":"https://openalex.org/C126445297","wikidata":"https://www.wikidata.org/wiki/Q8065380","display_name":"NOR gate","level":4,"score":0.4365110993385315},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.37441468238830566},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3631182909011841},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3215790390968323},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2884587049484253},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.24174648523330688},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.17249217629432678},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.15362629294395447},{"id":"https://openalex.org/C2361726","wikidata":"https://www.wikidata.org/wiki/Q5527031","display_name":"Gate oxide","level":4,"score":0.1165216863155365},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2015.7169014","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2015.7169014","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.5400000214576721}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2093085569","https://openalex.org/W2100272847","https://openalex.org/W2154930846"],"related_works":["https://openalex.org/W1017999001","https://openalex.org/W4361799621","https://openalex.org/W4295177619","https://openalex.org/W1987908008","https://openalex.org/W2248920447","https://openalex.org/W2134806353","https://openalex.org/W1521301810","https://openalex.org/W1996743178","https://openalex.org/W2153106046","https://openalex.org/W1487631000"],"abstract_inverted_index":{"Analysis":[0],"of":[1,4,33,66,87],"the":[2,21,24,30,34,39,63,67,77,81,85],"operation":[3],"CMOS":[5,45],"gates":[6,12,46],"is":[7,47,52,73],"a":[8],"complicated":[9],"procedure.":[10],"These":[11],"can":[13],"be":[14],"replaced":[15],"by":[16],"equivalent":[17,40,68],"inverters":[18,25],"and":[19],"therefore":[20],"expressions":[22,58],"for":[23,43,54,75],"are":[26,59],"used":[27,53,74],"to":[28,61],"determine":[29,62],"electrical":[31],"characteristics":[32],"gates.":[35],"In":[36],"this":[37,55,88],"paper,":[38],"inverter":[41],"approach":[42],"replacing":[44],"evaluated.":[48],"The":[49],"NAND":[50],"gate":[51],"evaluation.":[56],"Parametric":[57],"created":[60],"transistors":[64],"widths":[65],"inverter.":[69],"A":[70],"systematic":[71],"method":[72],"incorporating":[76],"parameter":[78],"dependencies":[79],"in":[80],"expressions.":[82],"Results":[83],"verify":[84],"accuracy":[86],"approach.":[89]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}