{"id":"https://openalex.org/W1484446114","doi":"https://doi.org/10.1109/iscas.2015.7168661","title":"A shared polyhedral cache for 3D wide-I/O multi-core computing platforms","display_name":"A shared polyhedral cache for 3D wide-I/O multi-core computing platforms","publication_year":2015,"publication_date":"2015-05-01","ids":{"openalex":"https://openalex.org/W1484446114","doi":"https://doi.org/10.1109/iscas.2015.7168661","mag":"1484446114"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2015.7168661","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2015.7168661","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089051890","display_name":"Mihai Lefter","orcid":null},"institutions":[{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Mihai Lefter","raw_affiliation_strings":["Faculty of EE, University of Technology, Delft, The Netherlands","Faculty of EE, Mathematics and CS, Computer Engineering Laboratory, Delft University of Technology, Delft, The Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of EE, University of Technology, Delft, The Netherlands","institution_ids":["https://openalex.org/I98358874"]},{"raw_affiliation_string":"Faculty of EE, Mathematics and CS, Computer Engineering Laboratory, Delft University of Technology, Delft, The Netherlands","institution_ids":["https://openalex.org/I98358874"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088271867","display_name":"George Voicu","orcid":null},"institutions":[{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"George Razvan Voicu","raw_affiliation_strings":["Faculty of EE, University of Technology, Delft, The Netherlands","Faculty of EE, Mathematics and CS, Computer Engineering Laboratory, Delft University of Technology, Delft, The Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of EE, University of Technology, Delft, The Netherlands","institution_ids":["https://openalex.org/I98358874"]},{"raw_affiliation_string":"Faculty of EE, Mathematics and CS, Computer Engineering Laboratory, Delft University of Technology, Delft, The Netherlands","institution_ids":["https://openalex.org/I98358874"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057424352","display_name":"Sorin Cot\u00f6fan\u0103","orcid":"https://orcid.org/0000-0001-7132-2291"},"institutions":[{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Sorin Dan Cotofana","raw_affiliation_strings":["Faculty of EE, University of Technology, Delft, The Netherlands","Faculty of EE, Mathematics and CS, Computer Engineering Laboratory, Delft University of Technology, Delft, The Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of EE, University of Technology, Delft, The Netherlands","institution_ids":["https://openalex.org/I98358874"]},{"raw_affiliation_string":"Faculty of EE, Mathematics and CS, Computer Engineering Laboratory, Delft University of Technology, Delft, The Netherlands","institution_ids":["https://openalex.org/I98358874"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I98358874"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"425","last_page":"428"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7372324466705322},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7284722328186035},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6702329516410828},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.5351957082748413},{"id":"https://openalex.org/keywords/memory-footprint","display_name":"Memory footprint","score":0.5121064186096191},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.38297808170318604},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.37308499217033386},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.34950345754623413},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.23122018575668335}],"concepts":[{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7372324466705322},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7284722328186035},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6702329516410828},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.5351957082748413},{"id":"https://openalex.org/C74912251","wikidata":"https://www.wikidata.org/wiki/Q6815727","display_name":"Memory footprint","level":2,"score":0.5121064186096191},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.38297808170318604},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.37308499217033386},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.34950345754623413},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.23122018575668335}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2015.7168661","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2015.7168661","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1515422725","https://openalex.org/W2071208935","https://openalex.org/W2105102111","https://openalex.org/W2109314689","https://openalex.org/W2122636510","https://openalex.org/W2125754106","https://openalex.org/W2126089060","https://openalex.org/W2131413854","https://openalex.org/W2136854849","https://openalex.org/W2150909864","https://openalex.org/W2160428323","https://openalex.org/W2464177207","https://openalex.org/W3139689176","https://openalex.org/W3146763006","https://openalex.org/W6682164510","https://openalex.org/W6719768283"],"related_works":["https://openalex.org/W2155019192","https://openalex.org/W2014709025","https://openalex.org/W2766970861","https://openalex.org/W3125341812","https://openalex.org/W1991674760","https://openalex.org/W1668171714","https://openalex.org/W2155297398","https://openalex.org/W4380607112","https://openalex.org/W2218294330","https://openalex.org/W1997278405"],"abstract_inverted_index":{"3D-Stacked":[0],"IC":[1],"(3D-SIC)":[2],"based":[3],"on":[4,39],"Through-Silicon-Vias":[5],"(TSV)":[6],"is":[7],"an":[8,107],"emerging":[9],"technology":[10],"that":[11,31,83],"enables":[12],"heterogeneous":[13],"integration":[14],"and":[15,96,106],"high":[16,100],"bandwidth":[17],"low":[18,102],"latency":[19],"interconnection.":[20],"In":[21],"this":[22],"paper":[23],"we":[24],"propose":[25],"a":[26,33,50,54,60,64],"3D":[27],"novel":[28],"cache":[29],"architecture":[30],"leverages":[32],"wide":[34],"TSV-based":[35],"data":[36,56,66],"link":[37],"distributed":[38],"the":[40,76],"entire":[41],"memory":[42],"array":[43],"to":[44],"support":[45],"two":[46],"orthogonal":[47],"interfaces:":[48],"(i)":[49],"vertical":[51],"one,":[52,62],"with":[53,63,69],"large":[55],"width,":[57,67],"and,":[58],"(ii)":[59],"side":[61],"lower":[65],"but":[68],"more":[70],"bank-type":[71],"access":[72,93,109],"ports,":[73],"which":[74],"reduces":[75],"bank":[77,103],"conflict":[78,104],"probability.":[79],"Our":[80],"simulations":[81],"indicate":[82],"our":[84],"proposal":[85],"substantially":[86],"outperforms":[87],"planar":[88],"counterparts":[89],"in":[90],"terms":[91],"of":[92],"time,":[94],"energy,":[95],"footprint":[97],"while":[98],"providing":[99],"bandwidth,":[101],"rate,":[105],"enriched":[108],"mechanism":[110],"set.":[111]},"counts_by_year":[{"year":2017,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
