{"id":"https://openalex.org/W1532299620","doi":"https://doi.org/10.1109/iscas.2015.7168598","title":"Automatic generation of inexact digital circuits by gate-level pruning","display_name":"Automatic generation of inexact digital circuits by gate-level pruning","publication_year":2015,"publication_date":"2015-05-01","ids":{"openalex":"https://openalex.org/W1532299620","doi":"https://doi.org/10.1109/iscas.2015.7168598","mag":"1532299620"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2015.7168598","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2015.7168598","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://infoscience.epfl.ch/record/210365","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090697759","display_name":"J\u00e9r\u00e9my Schlachter","orcid":"https://orcid.org/0000-0003-1483-3591"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Jeremy Schlachter","raw_affiliation_strings":["Integrated Circuits Laboratory (ICLAB), Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne, Switzerland","Integrated Circuits Laboratory (ICLAB), \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Switzerland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Circuits Laboratory (ICLAB), Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"Integrated Circuits Laboratory (ICLAB), \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073033950","display_name":"Vincent Camus","orcid":"https://orcid.org/0000-0003-4779-7742"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Vincent Camus","raw_affiliation_strings":["Integrated Circuits Laboratory (ICLAB), Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne, Switzerland","Integrated Circuits Laboratory (ICLAB), \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Switzerland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Circuits Laboratory (ICLAB), Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"Integrated Circuits Laboratory (ICLAB), \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069058393","display_name":"Christian Enz","orcid":"https://orcid.org/0000-0002-9968-5278"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Christian Enz","raw_affiliation_strings":["Integrated Circuits Laboratory (ICLAB), Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne, Switzerland","Integrated Circuits Laboratory (ICLAB), \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Switzerland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Circuits Laboratory (ICLAB), Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"Integrated Circuits Laboratory (ICLAB), \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5061421817","display_name":"Krishna V. Palem","orcid":null},"institutions":[{"id":"https://openalex.org/I74775410","display_name":"Rice University","ror":"https://ror.org/008zs3103","country_code":"US","type":"education","lineage":["https://openalex.org/I74775410"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Krishna V. Palem","raw_affiliation_strings":["Department of Computer Science, Rice University, Houston, TX, USA","Department of Computer Science, Rice University, Houston TX, 77005, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Rice University, Houston, TX, USA","institution_ids":["https://openalex.org/I74775410"]},{"raw_affiliation_string":"Department of Computer Science, Rice University, Houston TX, 77005, USA","institution_ids":["https://openalex.org/I74775410"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":5.7646,"has_fulltext":false,"cited_by_count":27,"citation_normalized_percentile":{"value":0.97258126,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"173","last_page":"176"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.7762741446495056},{"id":"https://openalex.org/keywords/pruning","display_name":"Pruning","score":0.7490062117576599},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7260813117027283},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6204915642738342},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5946151614189148},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5113010406494141},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5059084296226501},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.5043033361434937},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5036339163780212},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.45595836639404297},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.45102378726005554},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.44268685579299927},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.42706626653671265},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3798797130584717},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.29506248235702515},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.17712938785552979},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.16505631804466248},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1243206262588501},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09160935878753662}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.7762741446495056},{"id":"https://openalex.org/C108010975","wikidata":"https://www.wikidata.org/wiki/Q500094","display_name":"Pruning","level":2,"score":0.7490062117576599},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7260813117027283},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6204915642738342},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5946151614189148},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5113010406494141},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5059084296226501},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.5043033361434937},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5036339163780212},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.45595836639404297},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.45102378726005554},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.44268685579299927},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.42706626653671265},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3798797130584717},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.29506248235702515},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.17712938785552979},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.16505631804466248},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1243206262588501},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09160935878753662},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C6557445","wikidata":"https://www.wikidata.org/wiki/Q173113","display_name":"Agronomy","level":1,"score":0.0},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2015.7168598","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2015.7168598","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},{"id":"pmh:oai:infoscience.epfl.ch:210365","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/210365","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"}],"best_oa_location":{"id":"pmh:oai:infoscience.epfl.ch:210365","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/210365","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W588799346","https://openalex.org/W2092422952","https://openalex.org/W2104578404","https://openalex.org/W2106484393","https://openalex.org/W2109489315","https://openalex.org/W2135089667","https://openalex.org/W2151802820","https://openalex.org/W2155669548","https://openalex.org/W3141620748"],"related_works":["https://openalex.org/W2213903980","https://openalex.org/W3147061323","https://openalex.org/W2118796996","https://openalex.org/W2051008800","https://openalex.org/W2365114398","https://openalex.org/W2243815476","https://openalex.org/W2341264206","https://openalex.org/W3128899411","https://openalex.org/W2098419840","https://openalex.org/W2243536805"],"abstract_inverted_index":{"Inexact":[0],"or":[1],"approximate":[2],"circuits":[3,29,67],"show":[4],"great":[5],"ability":[6],"to":[7,19,42,63,96],"reduce":[8],"power":[9,102,116],"consumption":[10],"at":[11,92],"the":[12,25,43,51,80],"cost":[13],"of":[14,27,45,101,112],"occasional":[15],"errors":[16],"in":[17,79,99],"comparison":[18],"their":[20],"conventional":[21,71],"counterparts.":[22],"Even":[23],"though":[24],"benefits":[26],"such":[28],"have":[30],"been":[31],"proven":[32],"for":[33,120,128],"many":[34],"applications,":[35],"they":[36],"are":[37],"not":[38],"wide":[39],"spread":[40],"owing":[41],"absence":[44],"a":[46,61,70,121,129],"clear":[47],"design":[48,72,82],"methodology":[49,62],"and":[50,107,115],"required":[52],"CAD":[53],"tools.":[54],"In":[55],"this":[56,58,85],"regard,":[57],"paper":[59,86],"presents":[60],"automatically":[64],"generate":[65],"inexact":[66],"starting":[68],"from":[69],"by":[73],"adding":[74],"only":[75],"one":[76],"small":[77],"step":[78],"digital":[81],"flow.":[83],"Further,":[84],"also":[87],"demonstrates":[88],"that":[89],"achieving":[90],"pruning":[91],"gate-level":[93],"can":[94],"lead":[95],"substantial":[97],"savings":[98,117],"terms":[100],"consumption,":[103],"critical":[104],"path":[105],"delay":[106],"silicon":[108],"area.":[109],"An":[110],"order":[111],"magnitude":[113],"area":[114],"is":[118],"demonstrated":[119],"64-bit":[122],"gate":[123],"level":[124],"pruned":[125],"high-speed":[126],"adder":[127],"10%":[130],"relative":[131],"error":[132],"magnitude.":[133]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":4},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}