{"id":"https://openalex.org/W2165812548","doi":"https://doi.org/10.1109/iscas.2014.6865584","title":"A simple digital architecture for a harmonic-cancelling sine-wave synthesizer","display_name":"A simple digital architecture for a harmonic-cancelling sine-wave synthesizer","publication_year":2014,"publication_date":"2014-06-01","ids":{"openalex":"https://openalex.org/W2165812548","doi":"https://doi.org/10.1109/iscas.2014.6865584","mag":"2165812548"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2014.6865584","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2014.6865584","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039727177","display_name":"Pasindu Aluthwala","orcid":"https://orcid.org/0000-0002-2561-889X"},"institutions":[{"id":"https://openalex.org/I31746571","display_name":"UNSW Sydney","ror":"https://ror.org/03r8z3t63","country_code":"AU","type":"education","lineage":["https://openalex.org/I31746571"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"Pasindu Aluthwala","raw_affiliation_strings":["The University of New South Wales, NSW, Australia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of New South Wales, NSW, Australia","institution_ids":["https://openalex.org/I31746571"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001267886","display_name":"Neil Weste","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Neil Weste","raw_affiliation_strings":["NHEW R&D Pty Ltd"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NHEW R&D Pty Ltd","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043623579","display_name":"Andrew Adams","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Andrew Adams","raw_affiliation_strings":["Broadcom, Australia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Broadcom, Australia","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000792192","display_name":"Torsten Lehmann","orcid":null},"institutions":[{"id":"https://openalex.org/I31746571","display_name":"UNSW Sydney","ror":"https://ror.org/03r8z3t63","country_code":"AU","type":"education","lineage":["https://openalex.org/I31746571"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"Torsten Lehmann","raw_affiliation_strings":["The University of New South Wales, NSW, Australia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of New South Wales, NSW, Australia","institution_ids":["https://openalex.org/I31746571"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030042327","display_name":"Sri Parameswaran","orcid":"https://orcid.org/0000-0003-0435-9080"},"institutions":[{"id":"https://openalex.org/I31746571","display_name":"UNSW Sydney","ror":"https://ror.org/03r8z3t63","country_code":"AU","type":"education","lineage":["https://openalex.org/I31746571"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"Sri Parameswaran","raw_affiliation_strings":["The University of New South Wales, NSW, Australia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of New South Wales, NSW, Australia","institution_ids":["https://openalex.org/I31746571"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.9164,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.88083966,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"2113","last_page":"2116"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9955000281333923,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/spurious-free-dynamic-range","display_name":"Spurious-free dynamic range","score":0.8483180999755859},{"id":"https://openalex.org/keywords/direct-digital-synthesizer","display_name":"Direct digital synthesizer","score":0.7417070865631104},{"id":"https://openalex.org/keywords/sine-wave","display_name":"Sine wave","score":0.681969404220581},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6481723785400391},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6165433526039124},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5698876976966858},{"id":"https://openalex.org/keywords/sine","display_name":"Sine","score":0.4826570153236389},{"id":"https://openalex.org/keywords/digital-down-converter","display_name":"Digital down converter","score":0.4622843563556671},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.44814392924308777},{"id":"https://openalex.org/keywords/harmonic","display_name":"Harmonic","score":0.44128549098968506},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.38024574518203735},{"id":"https://openalex.org/keywords/dynamic-range","display_name":"Dynamic range","score":0.34545886516571045},{"id":"https://openalex.org/keywords/digital-signal","display_name":"Digital signal","score":0.285910427570343},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.28203123807907104},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2410421371459961},{"id":"https://openalex.org/keywords/frequency-synthesizer","display_name":"Frequency synthesizer","score":0.20197781920433044},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.16432487964630127},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.1446554958820343},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.1085989773273468},{"id":"https://openalex.org/keywords/acoustics","display_name":"Acoustics","score":0.10445466637611389}],"concepts":[{"id":"https://openalex.org/C119293636","wikidata":"https://www.wikidata.org/wiki/Q657480","display_name":"Spurious-free dynamic range","level":3,"score":0.8483180999755859},{"id":"https://openalex.org/C166089067","wikidata":"https://www.wikidata.org/wiki/Q1227465","display_name":"Direct digital synthesizer","level":5,"score":0.7417070865631104},{"id":"https://openalex.org/C66907618","wikidata":"https://www.wikidata.org/wiki/Q207527","display_name":"Sine wave","level":3,"score":0.681969404220581},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6481723785400391},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6165433526039124},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5698876976966858},{"id":"https://openalex.org/C186661526","wikidata":"https://www.wikidata.org/wiki/Q13647261","display_name":"Sine","level":2,"score":0.4826570153236389},{"id":"https://openalex.org/C99167442","wikidata":"https://www.wikidata.org/wiki/Q559292","display_name":"Digital down converter","level":4,"score":0.4622843563556671},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.44814392924308777},{"id":"https://openalex.org/C127934551","wikidata":"https://www.wikidata.org/wiki/Q1148098","display_name":"Harmonic","level":2,"score":0.44128549098968506},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.38024574518203735},{"id":"https://openalex.org/C87133666","wikidata":"https://www.wikidata.org/wiki/Q1161699","display_name":"Dynamic range","level":2,"score":0.34545886516571045},{"id":"https://openalex.org/C52773712","wikidata":"https://www.wikidata.org/wiki/Q175022","display_name":"Digital signal","level":3,"score":0.285910427570343},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.28203123807907104},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2410421371459961},{"id":"https://openalex.org/C182099602","wikidata":"https://www.wikidata.org/wiki/Q2660678","display_name":"Frequency synthesizer","level":4,"score":0.20197781920433044},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.16432487964630127},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.1446554958820343},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.1085989773273468},{"id":"https://openalex.org/C24890656","wikidata":"https://www.wikidata.org/wiki/Q82811","display_name":"Acoustics","level":1,"score":0.10445466637611389},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2014.6865584","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2014.6865584","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W605762311","https://openalex.org/W2002600803","https://openalex.org/W2053903311","https://openalex.org/W2055513287","https://openalex.org/W2127392716","https://openalex.org/W2147084331","https://openalex.org/W2148789349","https://openalex.org/W2159830952"],"related_works":["https://openalex.org/W2886467464","https://openalex.org/W2365874772","https://openalex.org/W2146470303","https://openalex.org/W2379854577","https://openalex.org/W2904790898","https://openalex.org/W2165824739","https://openalex.org/W2159932057","https://openalex.org/W3021352409","https://openalex.org/W2110751324","https://openalex.org/W2362063739"],"abstract_inverted_index":{"Sine-wave":[0],"synthesizers":[1,38],"are":[2],"a":[3,27,60,88],"core":[4],"requirement":[5],"in":[6],"many":[7],"electronic":[8,20],"applications,":[9],"such":[10],"as":[11],"communication":[12],"systems,":[13],"and":[14,16,33,71,94,107],"test":[15],"verification":[17],"of":[18,77],"analog/mixed-signal":[19],"systems.":[21],"In":[22,55],"sine-wave":[23,37,52],"synthesizers,":[24],"there":[25],"exists":[26],"compromise":[28],"between":[29],"output":[30,109],"spectral":[31],"purity":[32],"hardware":[34,47,63,69],"complexity.":[35],"Harmonic-cancelling":[36],"(HCSSs)":[39],"allow":[40],"spectrally":[41],"pure":[42],"signal":[43],"synthesis":[44,53],"at":[45],"low":[46],"cost,":[48],"compared":[49,74],"to":[50,75,115],"conventional":[51],"approaches.":[54],"this":[56],"paper,":[57],"we":[58],"propose":[59],"digital":[61],"HCSS":[62],"architecture,":[64],"which":[65],"is":[66],"simpler,":[67],"more":[68,72],"efficient":[70],"programmable":[73],"state":[76],"the":[78],"art":[79],"HCSSs.":[80],"The":[81],"proposed":[82],"architecture":[83],"has":[84],"been":[85],"verified":[86],"through":[87],"prototype":[89],"built":[90],"from":[91,112],"an":[92,108],"FPGA":[93],"discrete":[95],"components.":[96],"Prototype":[97],"results":[98],"demonstrate":[99],"51.9":[100],"dBc":[101],"spurious":[102],"free":[103],"dynamic":[104],"range":[105,111],"(SFDR)":[106],"frequency":[110],"100":[113,116],"Hz":[114],"kHz.":[117]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}