{"id":"https://openalex.org/W2001777089","doi":"https://doi.org/10.1109/iscas.2014.6865365","title":"Simulation-based memory dependence checker for CGRA-mapped code verification","display_name":"Simulation-based memory dependence checker for CGRA-mapped code verification","publication_year":2014,"publication_date":"2014-06-01","ids":{"openalex":"https://openalex.org/W2001777089","doi":"https://doi.org/10.1109/iscas.2014.6865365","mag":"2001777089"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2014.6865365","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2014.6865365","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111934929","display_name":"Heejun Shim","orcid":null},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Heejun Shim","raw_affiliation_strings":["Processor Architecture Lab, Samsung Advanced Institute of Technology (SAIT), Yongin, Korea","Processor Archit. Lab., Samsung Electron., Yongin, South Korea"],"affiliations":[{"raw_affiliation_string":"Processor Architecture Lab, Samsung Advanced Institute of Technology (SAIT), Yongin, Korea","institution_ids":["https://openalex.org/I2250650973"]},{"raw_affiliation_string":"Processor Archit. Lab., Samsung Electron., Yongin, South Korea","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109987997","display_name":"Soojung Ryu","orcid":null},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Soojung Ryu","raw_affiliation_strings":["Processor Architecture Lab, Samsung Advanced Institute of Technology (SAIT), Yongin, Korea","Processor Archit. Lab., Samsung Electron., Yongin, South Korea"],"affiliations":[{"raw_affiliation_string":"Processor Architecture Lab, Samsung Advanced Institute of Technology (SAIT), Yongin, Korea","institution_ids":["https://openalex.org/I2250650973"]},{"raw_affiliation_string":"Processor Archit. Lab., Samsung Electron., Yongin, South Korea","institution_ids":["https://openalex.org/I2250650973"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5111934929"],"corresponding_institution_ids":["https://openalex.org/I2250650973"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.07512861,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1235","last_page":"1238"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.877750039100647},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6239008903503418},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.5689687728881836},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.5543710589408875},{"id":"https://openalex.org/keywords/programmer","display_name":"Programmer","score":0.5045617818832397},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.42880114912986755},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4131931662559509},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3670402765274048},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.33877620100975037},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.32331815361976624},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.17698949575424194}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.877750039100647},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6239008903503418},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.5689687728881836},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.5543710589408875},{"id":"https://openalex.org/C2778514511","wikidata":"https://www.wikidata.org/wiki/Q1374194","display_name":"Programmer","level":2,"score":0.5045617818832397},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.42880114912986755},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4131931662559509},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3670402765274048},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33877620100975037},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.32331815361976624},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.17698949575424194},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2014.6865365","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2014.6865365","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/16","display_name":"Peace, Justice and strong institutions","score":0.6700000166893005}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W105298322","https://openalex.org/W1982399137","https://openalex.org/W2025787141","https://openalex.org/W2048742489","https://openalex.org/W2081662443","https://openalex.org/W2122992089","https://openalex.org/W2153056157","https://openalex.org/W2172130134","https://openalex.org/W3000710000","https://openalex.org/W4237625289"],"related_works":["https://openalex.org/W2379153735","https://openalex.org/W4244235824","https://openalex.org/W2168928134","https://openalex.org/W2112040168","https://openalex.org/W4241972157","https://openalex.org/W4242556954","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2944867581"],"abstract_inverted_index":{"In":[0,20,40],"a":[1,45,62,105,144],"coarse-grained":[2],"reconfigurable":[3],"array":[4],"(CGRA)":[5],"architecture,":[6],"software":[7],"pipelining":[8],"is":[9,35,51,93,109,124],"primarily":[10],"used":[11,52],"to":[12,37,75,99],"improve":[13],"performance":[14],"by":[15,95],"exploiting":[16],"loop-level":[17],"parallelism":[18],"(LLP).":[19],"this":[21,41],"technique,":[22],"the":[23,54,64,69,78,97,101,117,127,137,140],"loop-carried":[24],"memory":[25,47,65,88,106],"dependence":[26,48,89,107],"in":[27,53,126,149],"user":[28],"code":[29,142],"prevents":[30],"high":[31],"parallelism,":[32],"and":[33,72,136],"it":[34,74,82,131],"difficult":[36],"be":[38],"detected.":[39],"paper,":[42],"we":[43],"propose":[44],"simulation-based":[46],"checker,":[49],"which":[50],"verification":[55,86,133],"of":[56,68,77,87,139],"CGRA-mapped":[57,79,141],"code.":[58,80,103,120],"We":[59],"use":[60],"as":[61],"reference":[63],"access":[66],"behavior":[67],"sequential":[70,118],"processor":[71],"compare":[73],"that":[76],"Although":[81],"cannot":[83],"guarantee":[84],"perfect":[85],"violations,":[90],"our":[91,111,122],"approach":[92,112],"useful":[94],"guiding":[96],"programmer":[98],"modify":[100],"source":[102],"When":[104],"violation":[108],"detected,":[110],"provides":[113],"debugging":[114],"information":[115],"from":[116],"compiled":[119],"Moreover,":[121],"checker":[123],"implemented":[125],"register":[128],"transfer":[129],"level;":[130],"enables":[132],"time":[134],"reduction":[135],"testing":[138],"with":[143],"large":[145],"test":[146],"input":[147],"stream":[148],"FPGA":[150],"or":[151],"ASIC":[152],"implementations.":[153]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}