{"id":"https://openalex.org/W2003546312","doi":"https://doi.org/10.1109/iscas.2014.6865146","title":"A constructive approach for threshold logic circuit synthesis","display_name":"A constructive approach for threshold logic circuit synthesis","publication_year":2014,"publication_date":"2014-06-01","ids":{"openalex":"https://openalex.org/W2003546312","doi":"https://doi.org/10.1109/iscas.2014.6865146","mag":"2003546312"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2014.6865146","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2014.6865146","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033657866","display_name":"Augusto Neutzling","orcid":"https://orcid.org/0000-0001-6695-4710"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Augusto Neutzling","raw_affiliation_strings":["PPGC, Institute of Informatics, UFRGS, Porto Alegre, RS, Brazil","Inst. of Inf., UFRGS, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"PPGC, Institute of Informatics, UFRGS, Porto Alegre, RS, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"Inst. of Inf., UFRGS, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076835601","display_name":"Mayler G. A. Martins","orcid":"https://orcid.org/0000-0002-2848-2190"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Mayler G. A. Martins","raw_affiliation_strings":["PGMICRO, Institute of Informatics, UFRGS, Porto Alegre, RS, Brazil","Inst. of Inf., UFRGS, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"PGMICRO, Institute of Informatics, UFRGS, Porto Alegre, RS, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"Inst. of Inf., UFRGS, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090563366","display_name":"Renato P. Ribas","orcid":"https://orcid.org/0000-0002-9895-7489"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Renato P. Ribas","raw_affiliation_strings":["PGMICRO, Institute of Informatics, UFRGS, Porto Alegre, RS, Brazil","Inst. of Inf., UFRGS, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"PGMICRO, Institute of Informatics, UFRGS, Porto Alegre, RS, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"Inst. of Inf., UFRGS, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065397615","display_name":"Andr\u00e9 I. Reis","orcid":"https://orcid.org/0000-0002-3118-8160"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Andre I. Reis","raw_affiliation_strings":["PGMICRO, Institute of Informatics, UFRGS, Porto Alegre, RS, Brazil","Inst. of Inf., UFRGS, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"PGMICRO, Institute of Informatics, UFRGS, Porto Alegre, RS, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"Inst. of Inf., UFRGS, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I130442723"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"385","last_page":"388"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6574965119361877},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6237005591392517},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5958903431892395},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5579071640968323},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.545494019985199},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.5336718559265137},{"id":"https://openalex.org/keywords/constructive","display_name":"Constructive","score":0.5280547738075256},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5258054137229919},{"id":"https://openalex.org/keywords/resistor\u2013transistor-logic","display_name":"Resistor\u2013transistor logic","score":0.5223235487937927},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5190404057502747},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5178471207618713},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.509793221950531},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.42175859212875366},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.41946959495544434},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.38135862350463867},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.3640124201774597},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.280320405960083},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2552388608455658},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2240522801876068},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.18328320980072021},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1814185380935669}],"concepts":[{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6574965119361877},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6237005591392517},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5958903431892395},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5579071640968323},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.545494019985199},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.5336718559265137},{"id":"https://openalex.org/C2778701210","wikidata":"https://www.wikidata.org/wiki/Q28130034","display_name":"Constructive","level":3,"score":0.5280547738075256},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5258054137229919},{"id":"https://openalex.org/C180405849","wikidata":"https://www.wikidata.org/wiki/Q173464","display_name":"Resistor\u2013transistor logic","level":5,"score":0.5223235487937927},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5190404057502747},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5178471207618713},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.509793221950531},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.42175859212875366},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.41946959495544434},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.38135862350463867},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.3640124201774597},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.280320405960083},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2552388608455658},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2240522801876068},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.18328320980072021},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1814185380935669},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2014.6865146","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2014.6865146","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5699999928474426,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321091","display_name":"Coordena\u00e7\u00e3o de Aperfei\u00e7oamento de Pessoal de N\u00edvel Superior","ror":"https://ror.org/00x0ma614"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1511688816","https://openalex.org/W1609370892","https://openalex.org/W1662824729","https://openalex.org/W1969747706","https://openalex.org/W1991563000","https://openalex.org/W1994730253","https://openalex.org/W2043274724","https://openalex.org/W2111715689","https://openalex.org/W2117251208","https://openalex.org/W2147504239","https://openalex.org/W2155296713","https://openalex.org/W2162433640","https://openalex.org/W2196764267","https://openalex.org/W4237060324","https://openalex.org/W4238634207"],"related_works":["https://openalex.org/W2789662562","https://openalex.org/W2082591327","https://openalex.org/W2066518505","https://openalex.org/W2167525841","https://openalex.org/W2619968078","https://openalex.org/W2991771859","https://openalex.org/W1529529399","https://openalex.org/W1983370375","https://openalex.org/W1977171228","https://openalex.org/W2103473573"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"a":[3,30],"novel":[4],"method":[5],"to":[6,33,39,42,58,99,106],"synthesize":[7],"circuits":[8,37,86],"based":[9],"on":[10],"threshold":[11,24],"logic":[12,25,74],"gates":[13],"(TLG)":[14],"is":[15,20,56],"proposed.":[16],"Synthesis":[17],"considering":[18],"TLGs":[19],"quite":[21],"relevant,":[22],"since":[23],"has":[26],"been":[27],"revisited":[28],"as":[29,46],"promising":[31],"alternative":[32],"conventional":[34],"CMOS":[35],"integrated":[36],"due":[38],"its":[40],"suitability":[41],"emerging":[43],"technologies,":[44],"such":[45],"tunneling":[47],"diodes,":[48],"memristors":[49],"and":[50,68,76],"spintronics":[51],"devices.":[52],"A":[53],"constructive":[54],"process":[55],"applied":[57],"generate":[59],"optimized":[60],"TLG":[61],"networks":[62],"taking":[63],"into":[64],"account":[65],"multiple":[66],"goals":[67],"design":[69],"costs,":[70],"including":[71],"gate":[72,91],"count,":[73],"depth":[75],"number":[77],"of":[78,94],"interconnections.":[79],"Experiments":[80],"carried":[81],"out":[82],"over":[83],"MCNC":[84],"benchmark":[85],"have":[87],"shown":[88],"an":[89],"average":[90],"count":[92],"reduction":[93],"circa":[95],"32%,":[96],"reaching":[97],"up":[98],"54%":[100],"in":[101,104],"some":[102],"cases,":[103],"comparison":[105],"related":[107],"approaches.":[108]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
