{"id":"https://openalex.org/W2001817755","doi":"https://doi.org/10.1109/iscas.2013.6572022","title":"A power-efficient scan tree design by exploring the Q'-D connection","display_name":"A power-efficient scan tree design by exploring the Q'-D connection","publication_year":2013,"publication_date":"2013-05-01","ids":{"openalex":"https://openalex.org/W2001817755","doi":"https://doi.org/10.1109/iscas.2013.6572022","mag":"2001817755"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2013.6572022","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2013.6572022","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020614289","display_name":"Linfeng Chen","orcid":"https://orcid.org/0000-0002-0436-3197"},"institutions":[{"id":"https://openalex.org/I158809036","display_name":"Shenzhen Institute of Information Technology","ror":"https://ror.org/03wrf9427","country_code":"CN","type":"education","lineage":["https://openalex.org/I158809036"]},{"id":"https://openalex.org/I204983213","display_name":"Harbin Institute of Technology","ror":"https://ror.org/01yqg2h08","country_code":"CN","type":"education","lineage":["https://openalex.org/I204983213"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Linfeng Chen","raw_affiliation_strings":["School of Electronic and Information Engineering, Shenzhen Graduate School, Harbin Institute of Technology, Shenzhen, China","Shenzhen Grad. Sch., Sch. of Electron. & Inf. Eng., Harbin Inst. of Technol., Shenzhen, China"],"affiliations":[{"raw_affiliation_string":"School of Electronic and Information Engineering, Shenzhen Graduate School, Harbin Institute of Technology, Shenzhen, China","institution_ids":["https://openalex.org/I158809036","https://openalex.org/I204983213"]},{"raw_affiliation_string":"Shenzhen Grad. Sch., Sch. of Electron. & Inf. Eng., Harbin Inst. of Technol., Shenzhen, China","institution_ids":["https://openalex.org/I204983213"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5003304424","display_name":"Aijiao Cui","orcid":"https://orcid.org/0000-0002-4728-9265"},"institutions":[{"id":"https://openalex.org/I158809036","display_name":"Shenzhen Institute of Information Technology","ror":"https://ror.org/03wrf9427","country_code":"CN","type":"education","lineage":["https://openalex.org/I158809036"]},{"id":"https://openalex.org/I204983213","display_name":"Harbin Institute of Technology","ror":"https://ror.org/01yqg2h08","country_code":"CN","type":"education","lineage":["https://openalex.org/I204983213"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Aijiao Cui","raw_affiliation_strings":["School of Electronic and Information Engineering, Shenzhen Graduate School, Harbin Institute of Technology, Shenzhen, China","Shenzhen Grad. Sch., Sch. of Electron. & Inf. Eng., Harbin Inst. of Technol., Shenzhen, China"],"affiliations":[{"raw_affiliation_string":"School of Electronic and Information Engineering, Shenzhen Graduate School, Harbin Institute of Technology, Shenzhen, China","institution_ids":["https://openalex.org/I158809036","https://openalex.org/I204983213"]},{"raw_affiliation_string":"Shenzhen Grad. Sch., Sch. of Electron. & Inf. Eng., Harbin Inst. of Technol., Shenzhen, China","institution_ids":["https://openalex.org/I204983213"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5020614289"],"corresponding_institution_ids":["https://openalex.org/I158809036","https://openalex.org/I204983213"],"apc_list":null,"apc_paid":null,"fwci":1.2608,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.79323275,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1018","last_page":"1021"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9891999959945679,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scan-chain","display_name":"Scan chain","score":0.950371265411377},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.6896359920501709},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6838380098342896},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.615122377872467},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.4992971420288086},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.48238077759742737},{"id":"https://openalex.org/keywords/tree-structure","display_name":"Tree structure","score":0.46969082951545715},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.41745007038116455},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.27050715684890747},{"id":"https://openalex.org/keywords/binary-tree","display_name":"Binary tree","score":0.1765459179878235},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15762275457382202},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.15118485689163208},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10990989208221436},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.08063068985939026}],"concepts":[{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.950371265411377},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.6896359920501709},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6838380098342896},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.615122377872467},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.4992971420288086},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.48238077759742737},{"id":"https://openalex.org/C163797641","wikidata":"https://www.wikidata.org/wiki/Q2067937","display_name":"Tree structure","level":3,"score":0.46969082951545715},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.41745007038116455},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.27050715684890747},{"id":"https://openalex.org/C197855036","wikidata":"https://www.wikidata.org/wiki/Q380172","display_name":"Binary tree","level":2,"score":0.1765459179878235},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15762275457382202},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.15118485689163208},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10990989208221436},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.08063068985939026},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2013.6572022","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2013.6572022","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1820769975","https://openalex.org/W2004015493","https://openalex.org/W2037587557","https://openalex.org/W2041657610","https://openalex.org/W2090667189","https://openalex.org/W2108376128","https://openalex.org/W2116129521","https://openalex.org/W2116429369","https://openalex.org/W2119691242","https://openalex.org/W2138284668","https://openalex.org/W2156374538","https://openalex.org/W6680410900"],"related_works":["https://openalex.org/W2553035740","https://openalex.org/W2111928029","https://openalex.org/W1501621551","https://openalex.org/W2134712318","https://openalex.org/W2117171289","https://openalex.org/W2168885397","https://openalex.org/W1974621628","https://openalex.org/W1552599848","https://openalex.org/W2167571917","https://openalex.org/W2110102663"],"abstract_inverted_index":{"Full":[0],"scan":[1,29,38,47,63,72,78,89,101,112],"design":[2,65,108],"is":[3,80,118],"usually":[4],"time-consuming.":[5],"Scan":[6],"tree-based":[7],"architectures":[8],"can":[9,133],"be":[10,134],"applied":[11],"to":[12,37,56,111],"reduce":[13,57],"test":[14,59,131],"time,":[15],"but":[16],"few":[17],"of":[18,62,71,77,88,100],"them":[19],"are":[20,34],"power-efficient.":[21],"Many":[22],"low-power":[23,46],"techniques":[24],"have":[25],"been":[26],"proposed":[27],"for":[28,94],"chain":[30],"design,":[31,48],"while":[32],"they":[33],"not":[35,81],"applicable":[36],"tree":[39,64,79,90],"architecture.":[40],"To":[41],"achieve":[42],"a":[43,54],"time-efficient":[44],"and":[45],"in":[49],"this":[50],"paper,":[51],"we":[52],"propose":[53],"scheme":[55,84],"the":[58,68,75,83,86,98,106],"power":[60,96],"consumption":[61],"by":[66],"exploiting":[67],"Q'":[69],"ports":[70],"flip-flops.":[73],"As":[74],"structure":[76],"affected,":[82],"resembles":[85],"time-efficiency":[87],"design.":[91],"The":[92],"modification":[93],"low":[95],"maintains":[97],"order":[99],"cells.":[102],"It":[103],"thus":[104],"avoids":[105],"consequent":[107],"overhead":[109],"due":[110],"reordering.":[113],"Furthermore,":[114],"no":[115],"extra":[116],"hardware":[117],"introduced.":[119],"Experimental":[120],"results":[121],"on":[122,136],"ISCAS'89":[123],"benchmarks":[124],"show":[125],"that":[126],"8.38%":[127],"weighted":[128],"transitions":[129],"during":[130],"application":[132],"reduced":[135],"average.":[137]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}