{"id":"https://openalex.org/W1964643833","doi":"https://doi.org/10.1109/iscas.2013.6571792","title":"Trends on the application of emerging nonvolatile memory to processors and programmable devices","display_name":"Trends on the application of emerging nonvolatile memory to processors and programmable devices","publication_year":2013,"publication_date":"2013-05-01","ids":{"openalex":"https://openalex.org/W1964643833","doi":"https://doi.org/10.1109/iscas.2013.6571792","mag":"1964643833"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2013.6571792","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2013.6571792","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5029629432","display_name":"Lionel Torres","orcid":"https://orcid.org/0000-0001-5807-5070"},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I19894307","display_name":"Universit\u00e9 de Montpellier","ror":"https://ror.org/051escj72","country_code":"FR","type":"education","lineage":["https://openalex.org/I19894307"]},{"id":"https://openalex.org/I4210101743","display_name":"Laboratoire d'Informatique, de Robotique et de Micro\u00e9lectronique de Montpellier","ror":"https://ror.org/013yean28","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I151295451","https://openalex.org/I19894307","https://openalex.org/I4210101743","https://openalex.org/I4210159245","https://openalex.org/I4405261681"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Lionel Torres","raw_affiliation_strings":["LIRMM, CNRS, Universit\u00e9 Montpellier, Montpellier, France","LIRMM, Univ. Montpellier 2, Montpellier, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"LIRMM, CNRS, Universit\u00e9 Montpellier, Montpellier, France","institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I19894307","https://openalex.org/I4210101743"]},{"raw_affiliation_string":"LIRMM, Univ. Montpellier 2, Montpellier, France","institution_ids":["https://openalex.org/I19894307","https://openalex.org/I4210101743"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083599047","display_name":"Raphael M. Brum","orcid":"https://orcid.org/0000-0001-5317-4934"},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I19894307","display_name":"Universit\u00e9 de Montpellier","ror":"https://ror.org/051escj72","country_code":"FR","type":"education","lineage":["https://openalex.org/I19894307"]},{"id":"https://openalex.org/I4210101743","display_name":"Laboratoire d'Informatique, de Robotique et de Micro\u00e9lectronique de Montpellier","ror":"https://ror.org/013yean28","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I151295451","https://openalex.org/I19894307","https://openalex.org/I4210101743","https://openalex.org/I4210159245","https://openalex.org/I4405261681"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Raphael Martins Brum","raw_affiliation_strings":["LIRMM, CNRS, Universit\u00e9 Montpellier, Montpellier, France","LIRMM, Univ. Montpellier 2, Montpellier, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"LIRMM, CNRS, Universit\u00e9 Montpellier, Montpellier, France","institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I19894307","https://openalex.org/I4210101743"]},{"raw_affiliation_string":"LIRMM, Univ. Montpellier 2, Montpellier, France","institution_ids":["https://openalex.org/I19894307","https://openalex.org/I4210101743"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103272237","display_name":"Lu\u00eds Vit\u00f3rio Cargnini","orcid":"https://orcid.org/0000-0003-0580-5716"},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I19894307","display_name":"Universit\u00e9 de Montpellier","ror":"https://ror.org/051escj72","country_code":"FR","type":"education","lineage":["https://openalex.org/I19894307"]},{"id":"https://openalex.org/I4210101743","display_name":"Laboratoire d'Informatique, de Robotique et de Micro\u00e9lectronique de Montpellier","ror":"https://ror.org/013yean28","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I151295451","https://openalex.org/I19894307","https://openalex.org/I4210101743","https://openalex.org/I4210159245","https://openalex.org/I4405261681"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Luis Vitorio Cargnini","raw_affiliation_strings":["LIRMM, CNRS, Universit\u00e9 Montpellier, Montpellier, France","LIRMM, Univ. Montpellier 2, Montpellier, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"LIRMM, CNRS, Universit\u00e9 Montpellier, Montpellier, France","institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I19894307","https://openalex.org/I4210101743"]},{"raw_affiliation_string":"LIRMM, Univ. Montpellier 2, Montpellier, France","institution_ids":["https://openalex.org/I19894307","https://openalex.org/I4210101743"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013327343","display_name":"Gilles Sassatelli","orcid":"https://orcid.org/0000-0002-6396-286X"},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I19894307","display_name":"Universit\u00e9 de Montpellier","ror":"https://ror.org/051escj72","country_code":"FR","type":"education","lineage":["https://openalex.org/I19894307"]},{"id":"https://openalex.org/I4210101743","display_name":"Laboratoire d'Informatique, de Robotique et de Micro\u00e9lectronique de Montpellier","ror":"https://ror.org/013yean28","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I151295451","https://openalex.org/I19894307","https://openalex.org/I4210101743","https://openalex.org/I4210159245","https://openalex.org/I4405261681"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Gilles Sassatelli","raw_affiliation_strings":["LIRMM, CNRS, Universit\u00e9 Montpellier, Montpellier, France","LIRMM, Univ. Montpellier 2, Montpellier, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"LIRMM, CNRS, Universit\u00e9 Montpellier, Montpellier, France","institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I19894307","https://openalex.org/I4210101743"]},{"raw_affiliation_string":"LIRMM, Univ. Montpellier 2, Montpellier, France","institution_ids":["https://openalex.org/I19894307","https://openalex.org/I4210101743"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":26,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.7452660202980042},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7007328271865845},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6648244857788086},{"id":"https://openalex.org/keywords/magnetoresistive-random-access-memory","display_name":"Magnetoresistive random-access memory","score":0.6184879541397095},{"id":"https://openalex.org/keywords/non-volatile-random-access-memory","display_name":"Non-volatile random-access memory","score":0.5539919137954712},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5228779315948486},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.5001635551452637},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4881154000759125},{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.4717733860015869},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.45678648352622986},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.42629361152648926},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.3774797320365906},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.3686274290084839},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2802976667881012},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2551027536392212},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.2494933307170868},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.2091640830039978},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18202918767929077},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.16338974237442017},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.16080015897750854},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.0947449803352356},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08700406551361084}],"concepts":[{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.7452660202980042},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7007328271865845},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6648244857788086},{"id":"https://openalex.org/C46891859","wikidata":"https://www.wikidata.org/wiki/Q1061546","display_name":"Magnetoresistive random-access memory","level":3,"score":0.6184879541397095},{"id":"https://openalex.org/C34172316","wikidata":"https://www.wikidata.org/wiki/Q499024","display_name":"Non-volatile random-access memory","level":5,"score":0.5539919137954712},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5228779315948486},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.5001635551452637},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4881154000759125},{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.4717733860015869},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.45678648352622986},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.42629361152648926},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.3774797320365906},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.3686274290084839},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2802976667881012},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2551027536392212},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.2494933307170868},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.2091640830039978},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18202918767929077},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.16338974237442017},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.16080015897750854},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.0947449803352356},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08700406551361084},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2013.6571792","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2013.6571792","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:lirmm-00813631v1","is_oa":false,"landing_page_url":"https://hal-lirmm.ccsd.cnrs.fr/lirmm-00813631","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ISCAS: International Symposium on Circuits and Systems, May 2013, Beijing, China. pp.101-104, &#x27E8;10.1109/ISCAS.2013.6571792&#x27E9;","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8500000238418579,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320338463","display_name":"CHIST-ERA","ror":"https://ror.org/00rbzpz17"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1974370851","https://openalex.org/W1974956411","https://openalex.org/W1977773606","https://openalex.org/W2003390915","https://openalex.org/W2012923077","https://openalex.org/W2031539925","https://openalex.org/W2042525997","https://openalex.org/W2047379549","https://openalex.org/W2073091054","https://openalex.org/W2084007230","https://openalex.org/W2085743209","https://openalex.org/W2091685042","https://openalex.org/W2113398246","https://openalex.org/W2115885181","https://openalex.org/W2122171084","https://openalex.org/W2126107187","https://openalex.org/W2128644617","https://openalex.org/W2139580250","https://openalex.org/W2155925776","https://openalex.org/W2171051477","https://openalex.org/W2220434993","https://openalex.org/W3147376636","https://openalex.org/W3150512006","https://openalex.org/W3151493671"],"related_works":["https://openalex.org/W3194490625","https://openalex.org/W2372007526","https://openalex.org/W4386492288","https://openalex.org/W2107922524","https://openalex.org/W2189229908","https://openalex.org/W196405497","https://openalex.org/W2952379800","https://openalex.org/W1993178305","https://openalex.org/W4387251459","https://openalex.org/W3096220267"],"abstract_inverted_index":{"A":[0],"number":[1],"of":[2,18,56,80,94],"non-volatile":[3],"memory":[4,20,99],"technologies":[5],"(NVMs)":[6],"emerged":[7],"in":[8,42,65,96],"the":[9,43,69,78,92,97],"past":[10],"years.":[11,45],"They":[12],"promise":[13],"to":[14,83,91],"cope":[15],"with":[16],"limitations":[17],"standard":[19],"technologies,":[21],"such":[22],"as":[23],"scalability":[24],"and":[25,40,53,60],"idle":[26],"power":[27],"consumption.":[28],"Numerous":[29],"logic":[30,58],"circuits":[31,59],"based":[32,106],"on":[33,77,107],"these":[34,57],"emerging":[35],"technology":[36],"have":[37],"been":[38],"proposed":[39],"prototyped":[41],"last":[44],"In":[46,68],"this":[47,66,72],"paper,":[48],"we":[49,102,111],"present":[50],"an":[51],"overview":[52],"current":[54],"status":[55],"discuss":[61,103],"their":[62],"potential":[63,104],"applications":[64,105],"field.":[67],"first":[70],"part,":[71],"article":[73],"provides":[74],"a":[75,108],"survey":[76],"application":[79],"those":[81],"memories":[82],"programmable":[84],"devices.":[85],"The":[86],"second":[87],"section":[88],"is":[89],"dedicated":[90],"use":[93],"NVMs":[95],"processor's":[98],"hierarchy,":[100],"where":[101],"preliminary":[109],"study":[110],"performed.":[112],"Results":[113],"were":[114],"obtained":[115],"using":[116],"TAS-MRAM":[117],"NVM":[118],"technology.":[119]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":5},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-22T07:51:19.307946","created_date":"2025-10-10T00:00:00"}
