{"id":"https://openalex.org/W2048668733","doi":"https://doi.org/10.1109/iscas.2012.6272117","title":"Floorplan-aware hierarchical NoC topology with GALS interfaces","display_name":"Floorplan-aware hierarchical NoC topology with GALS interfaces","publication_year":2012,"publication_date":"2012-05-01","ids":{"openalex":"https://openalex.org/W2048668733","doi":"https://doi.org/10.1109/iscas.2012.6272117","mag":"2048668733"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2012.6272117","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2012.6272117","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113405673","display_name":"D\u00e9bora Matos","orcid":null},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Debora Matos","raw_affiliation_strings":["UFRGS Institute of Informatics, Porto Alegre, Brazil","UFRGS -- Institute of Informatics, Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"UFRGS Institute of Informatics, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"UFRGS -- Institute of Informatics, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019414171","display_name":"Cezar Reinbrecht","orcid":"https://orcid.org/0000-0001-6113-7041"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Cezar Reinbrecht","raw_affiliation_strings":["UFRGS Institute of Informatics, Porto Alegre, Brazil","UFRGS -- Institute of Informatics, Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"UFRGS Institute of Informatics, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"UFRGS -- Institute of Informatics, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077005193","display_name":"Gianluca Palermo","orcid":"https://orcid.org/0000-0001-7955-8012"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Gianluca Palermo","raw_affiliation_strings":["Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy","[Politecnico di Milano, Dipartimento di Elettronica e Informazione, Italy]"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]},{"raw_affiliation_string":"[Politecnico di Milano, Dipartimento di Elettronica e Informazione, Italy]","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089530145","display_name":"Jonathan Martinelli","orcid":"https://orcid.org/0000-0001-5386-9015"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Jonathan Martinelli","raw_affiliation_strings":["UFRGS Institute of Informatics, Porto Alegre, Brazil","UFRGS -- Institute of Informatics, Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"UFRGS Institute of Informatics, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"UFRGS -- Institute of Informatics, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043190662","display_name":"Altamiro Susin","orcid":"https://orcid.org/0000-0001-7034-5336"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Altamiro Susin","raw_affiliation_strings":["UFRGS Institute of Informatics, Porto Alegre, Brazil","UFRGS -- Institute of Informatics, Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"UFRGS Institute of Informatics, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"UFRGS -- Institute of Informatics, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031461662","display_name":"Cristina Silvano","orcid":"https://orcid.org/0000-0003-1668-0883"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Cristina Silvano","raw_affiliation_strings":["Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy","[Politecnico di Milano, Dipartimento di Elettronica e Informazione, Italy]"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]},{"raw_affiliation_string":"[Politecnico di Milano, Dipartimento di Elettronica e Informazione, Italy]","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5062358729","display_name":"Luigi Carro","orcid":"https://orcid.org/0000-0002-7402-4780"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Luigi Carro","raw_affiliation_strings":["UFRGS Institute of Informatics, Porto Alegre, Brazil","UFRGS -- Institute of Informatics, Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"UFRGS Institute of Informatics, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"UFRGS -- Institute of Informatics, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5113405673"],"corresponding_institution_ids":["https://openalex.org/I130442723"],"apc_list":null,"apc_paid":null,"fwci":1.4184,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.82648847,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"5","issue":null,"first_page":"652","last_page":"655"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10179","display_name":"Supercapacitor Materials and Fabrication","score":0.9954000115394592,"subfield":{"id":"https://openalex.org/subfields/2504","display_name":"Electronic, Optical and Magnetic Materials"},"field":{"id":"https://openalex.org/fields/25","display_name":"Materials Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9915000200271606,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.8145315647125244},{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.8112388849258423},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7413687705993652},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.6159892082214355},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5390493273735046},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5298357605934143},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.5231603384017944},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.5019080638885498},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.497010737657547},{"id":"https://openalex.org/keywords/dissipation","display_name":"Dissipation","score":0.49501556158065796},{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.4781378507614136},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.45064693689346313},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.4465908706188202},{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.4359095096588135},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4026558995246887},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.19260579347610474},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15396547317504883},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08944100141525269}],"concepts":[{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.8145315647125244},{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.8112388849258423},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7413687705993652},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.6159892082214355},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5390493273735046},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5298357605934143},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.5231603384017944},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.5019080638885498},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.497010737657547},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.49501556158065796},{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.4781378507614136},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.45064693689346313},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.4465908706188202},{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.4359095096588135},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4026558995246887},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.19260579347610474},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15396547317504883},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08944100141525269},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2012.6272117","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2012.6272117","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:re.public.polimi.it:11311/689887","is_oa":false,"landing_page_url":"http://hdl.handle.net/11311/689887","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8899999856948853}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W170689621","https://openalex.org/W178147422","https://openalex.org/W1567468802","https://openalex.org/W1973942054","https://openalex.org/W1974554881","https://openalex.org/W2027363446","https://openalex.org/W2036135729","https://openalex.org/W2056620549","https://openalex.org/W2076688601","https://openalex.org/W2104610013","https://openalex.org/W2124449277","https://openalex.org/W2126105956","https://openalex.org/W2130512670","https://openalex.org/W2136994107","https://openalex.org/W2140834004","https://openalex.org/W2148439970","https://openalex.org/W2151254834","https://openalex.org/W2166151045","https://openalex.org/W2167159964","https://openalex.org/W2170612559","https://openalex.org/W3112867862","https://openalex.org/W3152009116","https://openalex.org/W4214490465","https://openalex.org/W4236302577","https://openalex.org/W6607310143","https://openalex.org/W6678949850"],"related_works":["https://openalex.org/W1934552808","https://openalex.org/W2587830891","https://openalex.org/W1568494382","https://openalex.org/W4230458348","https://openalex.org/W3198758847","https://openalex.org/W2033923590","https://openalex.org/W2576538540","https://openalex.org/W1966325333","https://openalex.org/W2376124569","https://openalex.org/W2144357574"],"abstract_inverted_index":{"Networks-on-chip":[0],"has":[1],"been":[2],"seen":[3],"as":[4],"an":[5],"interconnect":[6],"solution":[7],"for":[8,20,30,77,107],"complex":[9],"systems.":[10],"However,":[11],"performance":[12],"and":[13,40,71,100],"energy":[14],"issues":[15],"still":[16],"represent":[17],"limiting":[18],"factors":[19],"Multi-Processors":[21],"System-on-Chip":[22],"(MPSoC).":[23],"Complex":[24],"router":[25],"architectures":[26],"can":[27,91],"be":[28],"prohibitive":[29],"the":[31,72,93,101,108],"embedded":[32],"domain,":[33],"once":[34],"they":[35],"dissipate":[36],"too":[37],"much":[38],"power":[39,49,94],"energy.":[41],"In":[42],"this":[43],"paper":[44],"we":[45],"propose":[46],"a":[47,61,114],"low":[48],"hierarchical":[50],"network":[51],"topology":[52],"with":[53,113],"GALS":[54],"interfaces,":[55],"allowing":[56],"each":[57,78],"cluster":[58,79],"operates":[59],"in":[60,96,103],"specific":[62],"frequency.":[63],"The":[64],"clusters":[65],"are":[66],"composed":[67],"by":[68],"crossbar":[69],"devices":[70],"number":[73],"of":[74],"cores":[75],"allocated":[76],"is":[80],"defined":[81],"considering":[82],"floorplan":[83],"information.":[84],"Experimental":[85],"results":[86],"show":[87],"that":[88],"our":[89],"strategy":[90],"reduce":[92],"dissipation":[95],"up":[97,104],"to":[98,105],"58%":[99],"latency":[102],"56%":[106],"benchmarks":[109],"analyzed":[110],"when":[111],"compared":[112],"packet-switched":[115],"mesh":[116],"network-on-chip.":[117]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}