{"id":"https://openalex.org/W2012519712","doi":"https://doi.org/10.1109/iscas.2012.6272096","title":"An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures","display_name":"An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures","publication_year":2012,"publication_date":"2012-05-01","ids":{"openalex":"https://openalex.org/W2012519712","doi":"https://doi.org/10.1109/iscas.2012.6272096","mag":"2012519712"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2012.6272096","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2012.6272096","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103232606","display_name":"Shinya Abe","orcid":"https://orcid.org/0000-0002-4353-7882"},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Shin-ya Abe","raw_affiliation_strings":["Department of Computer Science and Engineering, Waseda University, Japan","Dept. of Computer Science and Engineering, Waseda Univ., Japan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Waseda University, Japan","institution_ids":["https://openalex.org/I150744194"]},{"raw_affiliation_string":"Dept. of Computer Science and Engineering, Waseda Univ., Japan","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061982025","display_name":"Masao Yanagisawa","orcid":"https://orcid.org/0000-0002-5168-3214"},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masao Yanagisawa","raw_affiliation_strings":["Department of Computer Science and Engineering, Waseda University, Japan","Dept. of Computer Science and Engineering, Waseda Univ., Japan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Waseda University, Japan","institution_ids":["https://openalex.org/I150744194"]},{"raw_affiliation_string":"Dept. of Computer Science and Engineering, Waseda Univ., Japan","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5087516286","display_name":"Nozomu Togawa","orcid":"https://orcid.org/0000-0003-3400-3587"},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Nozomu Togawa","raw_affiliation_strings":["Department of Computer Science and Engineering, Waseda University, Japan","Dept. of Computer Science and Engineering, Waseda Univ., Japan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Waseda University, Japan","institution_ids":["https://openalex.org/I150744194"]},{"raw_affiliation_string":"Dept. of Computer Science and Engineering, Waseda Univ., Japan","institution_ids":["https://openalex.org/I150744194"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5103232606"],"corresponding_institution_ids":["https://openalex.org/I150744194"],"apc_list":null,"apc_paid":null,"fwci":2.0304,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.85928424,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":97},"biblio":{"volume":"3","issue":null,"first_page":"576","last_page":"579"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.8321443796157837},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7125279903411865},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6617425084114075},{"id":"https://openalex.org/keywords/converters","display_name":"Converters","score":0.6114843487739563},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5573599338531494},{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.5181618928909302},{"id":"https://openalex.org/keywords/efficient-energy-use","display_name":"Efficient energy use","score":0.5026428699493408},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4747355878353119},{"id":"https://openalex.org/keywords/energy","display_name":"Energy (signal processing)","score":0.4661608338356018},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.45150813460350037},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4431596100330353},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.43097859621047974},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.41961148381233215},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33150047063827515},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15584763884544373},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.14050382375717163},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.09266403317451477},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08009076118469238}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.8321443796157837},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7125279903411865},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6617425084114075},{"id":"https://openalex.org/C2778422915","wikidata":"https://www.wikidata.org/wiki/Q10302051","display_name":"Converters","level":3,"score":0.6114843487739563},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5573599338531494},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.5181618928909302},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.5026428699493408},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4747355878353119},{"id":"https://openalex.org/C186370098","wikidata":"https://www.wikidata.org/wiki/Q442787","display_name":"Energy (signal processing)","level":2,"score":0.4661608338356018},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.45150813460350037},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4431596100330353},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.43097859621047974},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.41961148381233215},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33150047063827515},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15584763884544373},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.14050382375717163},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.09266403317451477},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08009076118469238},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2012.6272096","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2012.6272096","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8799999952316284,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1501372902","https://openalex.org/W1999640823","https://openalex.org/W2037224163","https://openalex.org/W2082348718","https://openalex.org/W2103178253","https://openalex.org/W2116966184","https://openalex.org/W2154462472","https://openalex.org/W2158566102","https://openalex.org/W2161805663","https://openalex.org/W6675820861","https://openalex.org/W6683768037"],"related_works":["https://openalex.org/W3141861494","https://openalex.org/W2161004825","https://openalex.org/W2043900241","https://openalex.org/W2080729117","https://openalex.org/W1516038830","https://openalex.org/W2139708877","https://openalex.org/W2044534563","https://openalex.org/W2172010869","https://openalex.org/W2080804043","https://openalex.org/W1624807520"],"abstract_inverted_index":{"In":[0,54],"this":[1],"paper,":[2],"we":[3,21,28,94],"first":[4],"propose":[5,29],"a":[6],"huddle-based":[7],"distributed-register":[8,14,115],"architecture":[9,15],"(HDR":[10],"architecture),":[11],"an":[12,30],"island-based":[13],"for":[16,35],"multi-cycle":[17],"interconnect":[18],"communications":[19],"where":[20],"can":[22,95],"develop":[23],"several":[24],"energy-saving":[25,110],"techniques.":[26],"Next,":[27],"energy-efficient":[31,98],"high-level":[32,100],"synthesis":[33],"algorithm":[34,44,107],"HDR":[36],"architectures":[37,116],"focusing":[38],"on":[39,47],"multiple":[40],"supply":[41,82,89],"voltages.":[42],"Our":[43],"is":[45,62],"based":[46],"iterative":[48],"improvement":[49],"of":[50,60,64],"scheduling/binding":[51],"and":[52,69,87,117],"floorplanning.":[53],"the":[55,113],"iteration":[56],"process,":[57],"huddles,":[58,93],"each":[59],"which":[61],"composed":[63],"functional":[65],"units,":[66],"registers,":[67],"controller,":[68],"level":[70],"converters,":[71],"are":[72],"very":[73],"naturally":[74],"generated":[75],"using":[76],"floorplanning":[77],"results.":[78],"By":[79],"assigning":[80],"high":[81],"voltage":[83,90],"to":[84,91],"critical":[85],"huddles":[86],"low":[88],"non-critical":[92],"finally":[96],"have":[97],"floorplan-aware":[99],"synthesis.":[101],"Experimental":[102],"results":[103],"show":[104],"that":[105],"our":[106],"achieves":[108],"45%":[109],"compared":[111],"with":[112],"conventional":[114,118],"algorithms.":[119]},"counts_by_year":[{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2012,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
