{"id":"https://openalex.org/W2078971946","doi":"https://doi.org/10.1109/iscas.2012.6272070","title":"Full-custom design of low leakage data preserving ground gated 6T SRAM cells to facilitate single-ended write operations","display_name":"Full-custom design of low leakage data preserving ground gated 6T SRAM cells to facilitate single-ended write operations","publication_year":2012,"publication_date":"2012-05-01","ids":{"openalex":"https://openalex.org/W2078971946","doi":"https://doi.org/10.1109/iscas.2012.6272070","mag":"2078971946"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2012.6272070","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2012.6272070","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5042636120","display_name":"Hailong Jiao","orcid":"https://orcid.org/0000-0002-2815-6168"},"institutions":[{"id":"https://openalex.org/I200769079","display_name":"Hong Kong University of Science and Technology","ror":"https://ror.org/00q4vv597","country_code":"HK","type":"education","lineage":["https://openalex.org/I200769079"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Hailong Jiao","raw_affiliation_strings":["Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Hong Kong, China","Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology  Clear Water Bay Kowloon Hong Kong"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Hong Kong, China","institution_ids":["https://openalex.org/I200769079"]},{"raw_affiliation_string":"Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology  Clear Water Bay Kowloon Hong Kong","institution_ids":["https://openalex.org/I200769079"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5042147600","display_name":"Volkan Kursun","orcid":"https://orcid.org/0000-0002-8050-1774"},"institutions":[{"id":"https://openalex.org/I200769079","display_name":"Hong Kong University of Science and Technology","ror":"https://ror.org/00q4vv597","country_code":"HK","type":"education","lineage":["https://openalex.org/I200769079"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Volkan Kursun","raw_affiliation_strings":["Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Hong Kong, China","Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology  Clear Water Bay Kowloon Hong Kong"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Hong Kong, China","institution_ids":["https://openalex.org/I200769079"]},{"raw_affiliation_string":"Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology  Clear Water Bay Kowloon Hong Kong","institution_ids":["https://openalex.org/I200769079"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I200769079"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"484","last_page":"487"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.9138938188552856},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.7339670062065125},{"id":"https://openalex.org/keywords/sleep-mode","display_name":"Sleep mode","score":0.6797928214073181},{"id":"https://openalex.org/keywords/leakage-power","display_name":"Leakage power","score":0.6728577613830566},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5818231701850891},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5768685936927795},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5694643259048462},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4797005355358124},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.4794701337814331},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4749206006526947},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.3518993854522705},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3267548382282257},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.30213263630867004},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.27169156074523926},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23891538381576538},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1951097548007965},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.07673051953315735}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.9138938188552856},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.7339670062065125},{"id":"https://openalex.org/C57149124","wikidata":"https://www.wikidata.org/wiki/Q587346","display_name":"Sleep mode","level":4,"score":0.6797928214073181},{"id":"https://openalex.org/C2987719587","wikidata":"https://www.wikidata.org/wiki/Q1811428","display_name":"Leakage power","level":4,"score":0.6728577613830566},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5818231701850891},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5768685936927795},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5694643259048462},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4797005355358124},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.4794701337814331},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4749206006526947},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.3518993854522705},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3267548382282257},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.30213263630867004},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.27169156074523926},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23891538381576538},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1951097548007965},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.07673051953315735},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2012.6272070","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2012.6272070","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8899999856948853,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2128069289","https://openalex.org/W2142689656","https://openalex.org/W2155275912","https://openalex.org/W2496254462","https://openalex.org/W3213104937","https://openalex.org/W6682981187"],"related_works":["https://openalex.org/W2297319780","https://openalex.org/W2127524870","https://openalex.org/W1990717036","https://openalex.org/W2178217057","https://openalex.org/W1909296377","https://openalex.org/W1505213511","https://openalex.org/W1972800815","https://openalex.org/W2159770326","https://openalex.org/W1505038800","https://openalex.org/W1980741586"],"abstract_inverted_index":{"An":[0],"asymmetrically":[1,53,105],"ground-gated":[2,54,67,89,106],"six-transistor":[3],"(6T)":[4],"SRAM":[5,56,95,108],"circuit":[6,57,70],"is":[7,30,41,100],"presented":[8,101],"in":[9,58],"this":[10],"paper":[11],"for":[12,110],"providing":[13],"a":[14,50,59,88],"low":[15],"leakage":[16,80],"data":[17,73],"preserving":[18],"SLEEP":[19],"mode.":[20],"By":[21],"employing":[22],"multiple":[23],"write":[24,28,38],"assist":[25],"techniques,":[26],"the":[27,37,65,72,79,104,112],"margin":[29],"enhanced":[31],"by":[32,43,75,83],"up":[33,44],"to":[34,45,87,102],"2.73x":[35],"and":[36,77],"access":[39],"time":[40],"reduced":[42],"57.45%":[46],"as":[47,85],"compared":[48,86],"with":[49,92],"previously":[51],"published":[52],"6T":[55,68,94,107],"TSMC":[60],"65nm":[61],"CMOS":[62],"technology.":[63],"Furthermore,":[64],"new":[66],"memory":[69,90],"enhances":[71],"stability":[74],"2.09x":[76],"reduces":[78],"power":[81],"consumption":[82],"58.55%":[84],"array":[91],"conventional":[93],"cells.":[96],"A":[97],"design":[98],"methodology":[99],"optimize":[103],"circuits":[109],"achieving":[111],"highest":[113],"overall":[114],"electrical":[115],"quality.":[116]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}