{"id":"https://openalex.org/W1998888015","doi":"https://doi.org/10.1109/iscas.2012.6271969","title":"Multi-purpose systems: A novel dataflow-based generation and mapping strategy","display_name":"Multi-purpose systems: A novel dataflow-based generation and mapping strategy","publication_year":2012,"publication_date":"2012-05-01","ids":{"openalex":"https://openalex.org/W1998888015","doi":"https://doi.org/10.1109/iscas.2012.6271969","mag":"1998888015"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2012.6271969","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2012.6271969","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108645087","display_name":"Jean Fran\u00e7ois Nezan","orcid":null},"institutions":[{"id":"https://openalex.org/I126425946","display_name":"Universit\u00e9 Europ\u00e9enne de Bretagne","ror":"https://ror.org/033c46s90","country_code":"FR","type":"education","lineage":["https://openalex.org/I126425946"]},{"id":"https://openalex.org/I4210100151","display_name":"Institut d'\u00c9lectronique et des Technologies du num\u00e9Rique","ror":"https://ror.org/013q33h79","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I28221208","https://openalex.org/I4210095849","https://openalex.org/I4210100151","https://openalex.org/I56067802","https://openalex.org/I97188460"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"J.-F. Nezan","raw_affiliation_strings":["INSA, IETR, UMR 6164, European university of Brittany, Rennes, France","European University of Brittany, France, INSA, IETR, UMR 6164, F-35708 Rennes"],"affiliations":[{"raw_affiliation_string":"INSA, IETR, UMR 6164, European university of Brittany, Rennes, France","institution_ids":["https://openalex.org/I126425946","https://openalex.org/I4210100151"]},{"raw_affiliation_string":"European University of Brittany, France, INSA, IETR, UMR 6164, F-35708 Rennes","institution_ids":["https://openalex.org/I126425946","https://openalex.org/I4210100151"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026531279","display_name":"Nicolas Siret","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133574","display_name":"Elveflow (France)","ror":"https://ror.org/03cgw6h63","country_code":"FR","type":"company","lineage":["https://openalex.org/I4210133574"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"N. Siret","raw_affiliation_strings":["Synflow, France","Synflow, France, 50C rue Papu, 35000 RENNES"],"affiliations":[{"raw_affiliation_string":"Synflow, France","institution_ids":["https://openalex.org/I4210133574"]},{"raw_affiliation_string":"Synflow, France, 50C rue Papu, 35000 RENNES","institution_ids":["https://openalex.org/I4210133574"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091571029","display_name":"Matthieu Wipliez","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133574","display_name":"Elveflow (France)","ror":"https://ror.org/03cgw6h63","country_code":"FR","type":"company","lineage":["https://openalex.org/I4210133574"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"M. Wipliez","raw_affiliation_strings":["Synflow, France","Synflow, France, 50C rue Papu, 35000 RENNES"],"affiliations":[{"raw_affiliation_string":"Synflow, France","institution_ids":["https://openalex.org/I4210133574"]},{"raw_affiliation_string":"Synflow, France, 50C rue Papu, 35000 RENNES","institution_ids":["https://openalex.org/I4210133574"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028624281","display_name":"Francesca Palumbo","orcid":"https://orcid.org/0000-0002-6155-1979"},"institutions":[{"id":"https://openalex.org/I172446870","display_name":"University of Cagliari","ror":"https://ror.org/003109y17","country_code":"IT","type":"education","lineage":["https://openalex.org/I172446870"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"F. Palumbo","raw_affiliation_strings":["DIEE, University of Cagliari, Cagliari, Italy","DIEE - University of Cagliari, Italy, Piazza D'Armi, 09123"],"affiliations":[{"raw_affiliation_string":"DIEE, University of Cagliari, Cagliari, Italy","institution_ids":["https://openalex.org/I172446870"]},{"raw_affiliation_string":"DIEE - University of Cagliari, Italy, Piazza D'Armi, 09123","institution_ids":["https://openalex.org/I172446870"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007761671","display_name":"Luigi Raffo","orcid":"https://orcid.org/0000-0001-9683-009X"},"institutions":[{"id":"https://openalex.org/I172446870","display_name":"University of Cagliari","ror":"https://ror.org/003109y17","country_code":"IT","type":"education","lineage":["https://openalex.org/I172446870"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"L. Raffo","raw_affiliation_strings":["DIEE, University of Cagliari, Cagliari, Italy","DIEE - University of Cagliari, Italy, Piazza D'Armi, 09123"],"affiliations":[{"raw_affiliation_string":"DIEE, University of Cagliari, Cagliari, Italy","institution_ids":["https://openalex.org/I172446870"]},{"raw_affiliation_string":"DIEE - University of Cagliari, Italy, Piazza D'Armi, 09123","institution_ids":["https://openalex.org/I172446870"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5108645087"],"corresponding_institution_ids":["https://openalex.org/I126425946","https://openalex.org/I4210100151"],"apc_list":null,"apc_paid":null,"fwci":2.0304,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.85769159,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"2006","issue":null,"first_page":"3073","last_page":"3076"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.9690303802490234},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8430373668670654},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.7299790382385254},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.7092419862747192},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6552433967590332},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5640168786048889},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5301666259765625},{"id":"https://openalex.org/keywords/dataflow-architecture","display_name":"Dataflow architecture","score":0.519677460193634},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.519277811050415},{"id":"https://openalex.org/keywords/data-flow-analysis","display_name":"Data-flow analysis","score":0.5123394727706909},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5044316053390503},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5004768371582031},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.46678626537323},{"id":"https://openalex.org/keywords/data-flow-diagram","display_name":"Data flow diagram","score":0.44750508666038513},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.44116345047950745},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.43538546562194824},{"id":"https://openalex.org/keywords/model-of-computation","display_name":"Model of computation","score":0.41492778062820435},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.41203588247299194},{"id":"https://openalex.org/keywords/compile-time","display_name":"Compile time","score":0.41078630089759827},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2208327054977417},{"id":"https://openalex.org/keywords/database","display_name":"Database","score":0.10350146889686584}],"concepts":[{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.9690303802490234},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8430373668670654},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.7299790382385254},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.7092419862747192},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6552433967590332},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5640168786048889},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5301666259765625},{"id":"https://openalex.org/C176727019","wikidata":"https://www.wikidata.org/wiki/Q1172415","display_name":"Dataflow architecture","level":3,"score":0.519677460193634},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.519277811050415},{"id":"https://openalex.org/C88468194","wikidata":"https://www.wikidata.org/wiki/Q1172416","display_name":"Data-flow analysis","level":3,"score":0.5123394727706909},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5044316053390503},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5004768371582031},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.46678626537323},{"id":"https://openalex.org/C489000","wikidata":"https://www.wikidata.org/wiki/Q747385","display_name":"Data flow diagram","level":2,"score":0.44750508666038513},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.44116345047950745},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.43538546562194824},{"id":"https://openalex.org/C184596265","wikidata":"https://www.wikidata.org/wiki/Q2651576","display_name":"Model of computation","level":3,"score":0.41492778062820435},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.41203588247299194},{"id":"https://openalex.org/C200833197","wikidata":"https://www.wikidata.org/wiki/Q333707","display_name":"Compile time","level":3,"score":0.41078630089759827},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2208327054977417},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.10350146889686584},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2012.6271969","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2012.6271969","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:iris.unica.it:11584/103418","is_oa":false,"landing_page_url":"http://hdl.handle.net/11584/103418","pdf_url":null,"source":{"id":"https://openalex.org/S4377196293","display_name":"UNICA IRIS Institutional Research Information System (University of Cagliari)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I172446870","host_organization_name":"University of Cagliari","host_organization_lineage":["https://openalex.org/I172446870"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferencePaper"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.6399999856948853}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W90314788","https://openalex.org/W2009674297","https://openalex.org/W2029823978","https://openalex.org/W2029891867","https://openalex.org/W2117678124","https://openalex.org/W2132457452","https://openalex.org/W2166613240","https://openalex.org/W2169756956","https://openalex.org/W2482246557","https://openalex.org/W3005473396"],"related_works":["https://openalex.org/W2277357125","https://openalex.org/W2077180914","https://openalex.org/W4229975623","https://openalex.org/W2119685308","https://openalex.org/W2188794726","https://openalex.org/W2108674173","https://openalex.org/W2032571270","https://openalex.org/W1533244915","https://openalex.org/W4388501905","https://openalex.org/W1560380015"],"abstract_inverted_index":{"The":[0],"manual":[1],"creation":[2],"of":[3,17,46,55,58,75,85],"specialized":[4],"hard-ware":[5],"infrastructures":[6],"for":[7],"complex":[8],"multi-purpose":[9,78],"systems":[10],"is":[11,19],"error-prone":[12],"and":[13,25,65,80,93,100],"time-consuming.":[14],"Moreover,":[15],"lots":[16],"effort":[18],"required":[20],"to":[21],"define":[22],"an":[23],"optimized":[24],"heterogeneous":[26],"components":[27],"library.":[28],"To":[29],"tackle":[30],"these":[31],"issues,":[32],"we":[33,50],"propose":[34],"a":[35,76],"novel":[36],"design":[37],"flow":[38],"based":[39],"on":[40,98],"the":[41,53,59,62,66,72,81],"Dataflow":[42],"Process":[43],"Networks":[44],"Model":[45],"Computation.":[47],"In":[48],"particular,":[49],"have":[51],"combined":[52],"operation":[54],"two":[56],"state":[57],"art":[60],"tools,":[61],"Multi-Dataflow":[63],"Composer":[64],"Open":[67],"RVC-CAL":[68],"Compiler,":[69],"handling":[70],"respectively":[71],"automatic":[73],"mapping":[74],"reconfigurable":[77],"substrate":[79],"high":[82],"level":[83],"synthesis":[84],"hardware":[86],"components.":[87],"Our":[88],"approach":[89],"guarantees":[90],"runtime":[91],"efficiency":[92],"on-chip":[94],"area":[95],"saving":[96],"both":[97],"FPGAs":[99],"ASICs.":[101]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":5},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2016-06-24T00:00:00"}