{"id":"https://openalex.org/W2062560178","doi":"https://doi.org/10.1109/iscas.2012.6271621","title":"A comparative study on asynchronous Quasi-Delay-Insensitive templates","display_name":"A comparative study on asynchronous Quasi-Delay-Insensitive templates","publication_year":2012,"publication_date":"2012-05-01","ids":{"openalex":"https://openalex.org/W2062560178","doi":"https://doi.org/10.1109/iscas.2012.6271621","mag":"2062560178"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2012.6271621","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2012.6271621","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020890655","display_name":"Kok-Leong Chang","orcid":null},"institutions":[{"id":"https://openalex.org/I4210123095","display_name":"Institute of Materials Research and Engineering","ror":"https://ror.org/02sepg748","country_code":"SG","type":"facility","lineage":["https://openalex.org/I115228651","https://openalex.org/I4210123095","https://openalex.org/I91275662"]},{"id":"https://openalex.org/I115228651","display_name":"Agency for Science, Technology and Research","ror":"https://ror.org/036wvzt09","country_code":"SG","type":"government","lineage":["https://openalex.org/I115228651"]}],"countries":["SG"],"is_corresponding":true,"raw_author_name":"Kok-Leong Chang","raw_affiliation_strings":["Synthesis and Integration, Institute of Materials Research and Engineering (IMRE), Agency for Science, Technology and Research, Singapore","Synthesis and Integration, Institute of Materials Research and Engineering (IMRE), A\u2217STAR, Singapore"],"affiliations":[{"raw_affiliation_string":"Synthesis and Integration, Institute of Materials Research and Engineering (IMRE), Agency for Science, Technology and Research, Singapore","institution_ids":["https://openalex.org/I115228651","https://openalex.org/I4210123095"]},{"raw_affiliation_string":"Synthesis and Integration, Institute of Materials Research and Engineering (IMRE), A\u2217STAR, Singapore","institution_ids":["https://openalex.org/I115228651"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101677729","display_name":"Tong Lin","orcid":"https://orcid.org/0000-0002-8112-0439"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Tong Lin","raw_affiliation_strings":["Centre for Integrated Circuits and Systems, Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"Centre for Integrated Circuits and Systems, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014926180","display_name":"Weng\u2010Geng Ho","orcid":"https://orcid.org/0000-0002-0589-3480"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Weng-Geng Ho","raw_affiliation_strings":["Centre for Integrated Circuits and Systems, Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"Centre for Integrated Circuits and Systems, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073268696","display_name":"Kwen\u2010Siong Chong","orcid":"https://orcid.org/0000-0003-1512-2003"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Kwen-Siong Chong","raw_affiliation_strings":["Centre for Integrated Circuits and Systems, Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"Centre for Integrated Circuits and Systems, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000314679","display_name":"Bah\u2010Hwee Gwee","orcid":"https://orcid.org/0000-0002-3222-2885"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Bah-Hwee Gwee","raw_affiliation_strings":["Centre for Integrated Circuits and Systems, Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"Centre for Integrated Circuits and Systems, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5023352317","display_name":"Joseph S. Chang","orcid":"https://orcid.org/0000-0003-0991-8339"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Joseph S. Chang","raw_affiliation_strings":["Centre for Integrated Circuits and Systems, Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"Centre for Integrated Circuits and Systems, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5020890655"],"corresponding_institution_ids":["https://openalex.org/I115228651","https://openalex.org/I4210123095"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.12066533,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1819","last_page":"1822"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.9175876975059509},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.7257076501846313},{"id":"https://openalex.org/keywords/template","display_name":"Template","score":0.7224172353744507},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7148916721343994},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.6795409917831421},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5047467947006226},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4489325284957886},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.43752825260162354},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.4250800609588623},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.41425561904907227},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4011135697364807},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3838449716567993},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.27070608735084534},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.20482686161994934},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1508522927761078},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1383225917816162},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13249996304512024},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13223162293434143}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.9175876975059509},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.7257076501846313},{"id":"https://openalex.org/C82714645","wikidata":"https://www.wikidata.org/wiki/Q438331","display_name":"Template","level":2,"score":0.7224172353744507},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7148916721343994},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.6795409917831421},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5047467947006226},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4489325284957886},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.43752825260162354},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.4250800609588623},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.41425561904907227},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4011135697364807},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3838449716567993},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.27070608735084534},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.20482686161994934},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1508522927761078},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1383225917816162},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13249996304512024},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13223162293434143},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2012.6271621","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2012.6271621","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:dr.ntu.edu.sg:10356/106111","is_oa":false,"landing_page_url":"https://hdl.handle.net/10356/106111","pdf_url":null,"source":{"id":"https://openalex.org/S4306402609","display_name":"DR-NTU (Nanyang Technological University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I172675005","host_organization_name":"Nanyang Technological University","host_organization_lineage":["https://openalex.org/I172675005"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference Paper"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1500359059","https://openalex.org/W1567324233","https://openalex.org/W1998380797","https://openalex.org/W2048762589","https://openalex.org/W2092892712","https://openalex.org/W2104105510","https://openalex.org/W2108964809","https://openalex.org/W2123081879","https://openalex.org/W2127514448","https://openalex.org/W2127819702","https://openalex.org/W2132339613","https://openalex.org/W2134829921","https://openalex.org/W2135664674","https://openalex.org/W2178247634","https://openalex.org/W6680056528"],"related_works":["https://openalex.org/W4247130854","https://openalex.org/W2165341302","https://openalex.org/W1984298705","https://openalex.org/W4212803501","https://openalex.org/W1482079447","https://openalex.org/W2127795343","https://openalex.org/W2098419840","https://openalex.org/W2109350679","https://openalex.org/W2140883893","https://openalex.org/W1966764473"],"abstract_inverted_index":{"The":[0,124],"robustness":[1],"of":[2,28,36,66,73,105,134],"asynchronous":[3,29,46,74,90],"logic":[4,30],"has":[5,31],"proved":[6],"useful":[7],"in":[8,13,57,83],"dealing":[9],"with":[10,63],"contemporary":[11],"problems":[12],"CMOS":[14],"design":[15,39,47,68,107],"such":[16],"as":[17],"process":[18],"variations":[19],"and":[20,99,118],"power":[21],"management.":[22],"However,":[23,61],"the":[24,33,42,49,64,86],"general":[25],"cryptic":[26],"nature":[27],"stymied":[32],"widespread":[34],"acceptance":[35],"this":[37,67,84],"alternate":[38],"technique.":[40],"Fortunately,":[41],"semi-custom":[43],"approach":[44,69],"to":[45,94],"reduces":[48],"tedious":[50],"handcrafting":[51],"efforts":[52],"that":[53,76],"are":[54],"often":[55],"non-trivial":[56],"large":[58],"system-on-chips":[59],"(SoCs).":[60],"even":[62],"adoption":[65],"requires":[70],"careful":[71],"selection":[72],"templates":[75],"will":[77,96],"suit":[78],"overall":[79],"system":[80],"needs.":[81],"Therefore":[82],"paper,":[85],"most":[87,125],"eminent":[88],"Quasi-Delay-Insensitive":[89],"template":[91,110,127],"families":[92],"reported":[93],"date":[95],"be":[97],"presented,":[98],"followed":[100],"by":[101],"an":[102],"in-depth":[103],"comparison":[104],"various":[106],"FOMs":[108],"-":[109],"area,":[111],"static/dynamic":[112],"capacity,":[113],"cycle":[114],"time,":[115],"latency,":[116],"throughput":[117,133],"Et":[119],"<sup":[120],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[121],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[122],".":[123],"aggressive":[126],"(EESTFB)":[128],"can":[129],"reach":[130],"a":[131],"maximum":[132],"3.56Giga":[135],"items/s":[136],"on":[137],"0.13\u00b5m":[138],"@":[139],"1.2V.":[140]},"counts_by_year":[{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}